ISPXPLD51024MX XPLD Datasheet

ISPXPLD51024MX Datasheet PDF, Equivalent


Part Number

ISPXPLD51024MX

Description

eXpanded Programmable Logic Device XPLD

Manufacture

Lattice Semiconductor

Total Page 30 Pages
PDF Download
Download ISPXPLD51024MX Datasheet PDF


ISPXPLD51024MX
ispXPLDTM 5000MX Family
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD™ Family
February 2010
Data Sheet
Features
Flexible Multi-Function Block (MFB)
Architecture
• SuperWIDE™ logic (up to 136 inputs)
• Arithmetic capability
• Single- or Dual-port SRAM
• FIFO
• Ternary CAM
sysCLOCK™ PLL Timing Control
• Multiply and divide between 1 and 32
• Clock shifting capability
• External feedback capability
sysIO™ Interfaces
• LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pull-
down, bus-keeper, or none)
– Open drain operation
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI 3.3
• GTL+
• LVDS
• LVPECL
• LVTTL
Table 1. ispXPLD 5000MX Family Selection Guide
Expanded In-System Programmability (ispXP™)
• Instant-on capability
• Single chip convenience
• In-System Programmable via IEEE 1532
Interface
• Infinitely reconfigurable via IEEE 1532 or sys-
CONFIG™ microprocessor interface
• Design security
High Speed Operation
• 4.0ns pin-to-pin delays, 300MHz fMAX
• Deterministic timing
Low Power Consumption
• Typical static power: 20 to 50mA (1.8V),
30 to 60mA (2.5/3.3V)
• 1.8V core for low dynamic power
Easy System Integration
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
• IEEE 1149.1 interface for boundary scan testing
• sysIO quick configuration
• Density migration
• Multiple density and package options
• PQFP and fine pitch BGA packaging
• Lead-free package options
Macrocells
Multi-Function Blocks
Maximum RAM Bits
Maximum CAM Bits
sysCLOCK PLLs
tPD (Propagation Delay)
tS (Register Set-up Time)
tCO (Register Clock to Out Time)
fMAX (Maximum Operating Frequency)
Functional Gates
I/Os
Packages
ispXPLD 5256MX
256
8
128K
48K
2
4.0ns
2.2ns
2.8ns
300MHz
75K
141
256 fpBGA
ispXPLD 5512MX
512
16
256K
96K
2
4.5ns
2.8ns
3.0ns
275MHz
150K
149/193/253
208 PQFP
256 fpBGA
484 fpBGA
ispXPLD 5768MX ispXPLD 51024MX
768 1,024
24 32
384K
512K
144K
192K
22
5.0ns
5.2ns
2.8ns
3.0ns
3.2ns
3.7ns
250MHz
250MHz
225K
300K
193/317
317/381
256 fpBGA
484 fpBGA
484 fpBGA
672 fpBGA
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
5kmx_12.4

ISPXPLD51024MX
Lattice Semiconductor
Figure 1. ispXPLD 5000MX Block Diagram
ispXPLD 5000MX Family Data Sheet
VCCO0
VREF0
sysIO
Bank 0
ISP Port
MFB
MFB
sysIO
Bank 3
VCCO3
VREF3
GCLCK0
VCCP
GNDP
GCLK1
sysCLOCK
PLL 0
sysIO
Bank 1
Optional
sysCONFIG
Interface
VREF1
VCCO1
MFB
MFB
MFB
Global
Routing
Pool
(GRP)
MFB
MFB
MFB
GCLCK3
sysCLOCK
PLL 1
sysIO
Bank 2
GCLK2
RESET
GOE0
GOE1
VREF2
VCCO2
Introduction
The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic
Devices (XPLDs). These devices extend the capability of Lattice’s popular SuperWIDE ispMACH 5000 architecture
by providing flexible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM
operation. Extra logic has also been included to allow efficient implementation of arithmetic functions. In addition,
sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers.
The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design
security, and extreme reconfigurability. The use of advanced process technology provides industry-leading perfor-
mance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and oper-
ating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The
ispXPLD 5000MX architecture provides predictable deterministic timing.
The availability of 3.3, 2.5 and 1.8V versions of these devices along with the flexibility of the sysIO interface helps
users meet the challenge of today’s mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O
bank is configured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases inte-
gration into today’s complex systems. A variety of density and package options increase the likelihood of a good fit
for a particular application. Table 1 shows the members of the ispXPLD 5000MX family.
Architecture
The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool.
Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD
2


Features DISSECLOENCTTINDUEEVIDCES ispXPLDTM 500 0MX Family 3.3V, 2.5V and 1.8V In-Syst em Programmable eXpanded Programmable L ogic Device XPLD™ Family February 20 10 Data Sheet Features  Flexible M ulti-Function Block (MFB) Architecture • SuperWIDE™ logic (up to 136 input s) • Arithmetic capability • Single - or Dual-port SRAM • FIFO • Ternar y CAM  sysCLOCK™ PLL Timing Contro l • Multiply and divide between 1 and 32 • Clock shifting capability • E xternal feedback capability  sysIO Interfaces • LVCMOS 1.8, 2.5, 3.3V – Programmable impedance – Hot-sock eting – Flexible bus-maintenance (Pul l-up, pulldown, bus-keeper, or none) Open drain operation • SSTL 2, 3 (I & II) • HSTL (I, III, IV) • PCI 3. 3 • GTL+ • LVDS • LVPECL • LVTT L Table 1. ispXPLD 5000MX Family Select ion Guide  Expanded In-System Progr ammability (ispXP™) • Instant-on ca pability • Single chip convenience In-System Programmable via IEEE 1532 Interface • Infinitely reconfigurable via IEEE 1532 or sys- CONFIG™ microprocessor inter.
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