LFXP6 gate Datasheet

LFXP6 Datasheet PDF, Equivalent


Part Number

LFXP6

Description

FPGA devices combine logic gate

Manufacture

Lattice Semiconductor

Total Page 30 Pages
PDF Download
Download LFXP6 Datasheet PDF


LFXP6
LatticeXP Family Data Sheet
DS1001 Version 05.1, November 2007

LFXP6
LatticeXP Family Data Sheet
Introduction
July 2007
Features
Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• No external configuration memory
• Excellent design security, no bit stream to
intercept
• Reconfigure SRAM based logic in milliseconds
• SRAM and non-volatile memory programmable
through system configuration and JTAG ports
Sleep Mode
• Allows up to 1000x static current reduction
TransFR™ Reconfiguration (TFR)
• In-field logic update while system operates
Extensive Density and Package Options
• 3.1K to 19.7K LUT4s
• 62 to 340 I/Os
• Density migration supported
Embedded and Distributed Memory
• 54 Kbits to 396 Kbits sysMEM™ Embedded
Block RAM
• Up to 79 Kbits distributed RAM
• Flexible memory resources:
Distributed and block memory
Data Sheet DS1001
Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
– SSTL 18 Class I
SSTL 3/2 Class I, II
– HSTL15 Class I, III
HSTL 18 Class I, II, III
PCI
LVDS, Bus-LVDS, LVPECL, RSDS
Dedicated DDR Memory Support
• Implements interface up to DDR333 (166MHz)
sysCLOCK™ PLLs
• Up to 4 analog PLLs per device
• Clock multiply, divide and phase shifting
System Level Support
• IEEE Standard 1149.1 Boundary Scan, plus
ispTRACY™ internal logic analyzer capability
• Onboard oscillator for configuration
• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
Table 1-1. LatticeXP Family Selection Guide
Device
LFXP3
LFXP6
PFU/PFF Rows
16 24
PFU/PFF Columns
24 30
PFU/PFF (Total)
384 720
LUTs (K)
36
Distributed RAM (KBits)
12
23
EBR SRAM (KBits)
54 72
EBR SRAM Blocks
68
VCC Voltage
PLLs
1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V
22
Max. I/O
136 188
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
62
144-pin TQFP (20 x 20 mm)
100
100
208-pin PQFP (28 x 28 mm)
136
142
256-ball fpBGA (17 x 17 mm)
188
388-ball fpBGA (23 x 23 mm)
484-ball fpBGA (23 x 23 mm)
LFXP10
32
38
1216
10
39
216
24
1.2/1.8/2.5/3.3V
4
244
188
244
LFXP15
40
48
1932
15
61
324
36
1.2/1.8/2.5/3.3V
4
300
188
268
300
LFXP20
44
56
2464
20
79
396
44
1.2/1.8/2.5/3.3V
4
340
188
268
340
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1 DS1001 Introduction_01.5


Features LatticeXP Family Data Sheet DS1001 Versi on 05.1, November 2007 LatticeXP Famil y Data Sheet Introduction July 2007 Fe atures  Non-volatile, Infinitely Rec onfigurable • Instant-on – powers u p in microseconds • No external confi guration memory • Excellent design se curity, no bit stream to  intercept • Reconfigure SRAM based logic in mil liseconds • SRAM and non-volatile mem ory programmable through system configu ration and JTAG ports  Sleep Mode Allows up to 1000x static current red uction  TransFR™ Reconfiguration ( TFR) • In-field logic update while sy stem operates  Extensive Density and Package Options • 3.1K to 19.7K LUT4 s • 62 to 340 I/Os • Density migrat ion supported  Embedded and Distribu ted Memory • 54 Kbits to 396 Kbits sy sMEM™ Embedded Block RAM • Up to 79 Kbits distributed RAM • Flexible mem ory resources:  Distributed and bloc k memory Data Sheet DS1001  Flexibl e I/O Buffer • Programmable sysIO™ buffer supports wide range of interfaces:  LVCMOS 3.3/2.5/1.8/1.5/1.2  LVT.
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