EP910 EPLD Datasheet

EP910 Datasheet PDF, Equivalent


Part Number

EP910

Description

EPLD

Manufacture

Altera

Total Page 30 Pages
PDF Download
Download EP910 Datasheet PDF


EP910
May 1999, ver. 5
Features
Classic
® EPLD Family
Data Sheet
s Complete device family with logic densities of 300 to 900 usable gates
(see Table 1)
s Device erasure and reprogramming with non-volatile EPROM
configuration elements
s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
s 24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
s Programmable security bit for protection of proprietary designs
s 100% generically tested to provide 100% programming yield
s Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
s Software design support featuring the Altera® MAX+PLUS® II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
s Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
s Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
Table 1. Classic Device Features
Feature
Usable gates
Macrocells
Maximum user I/O pins
tPD (ns)
fCNT (MHz)
EP610
EP610I
300
16
22
10
100
EP910
EP910I
450
24
38
12
76.9
EP1810
900
48
64
20
50
Altera Corporation
A-DS-CLASSIC-05
745

EP910
Classic EPLD Family Data Sheet
General
Description
The Altera ClassicTM device family offers a solution to high-speed, low-
power logic integration. Fabricated on advanced CMOS technology,
Classic devices also have a Turbo-only version, which is described in this
data sheet.
Classic devices support 100% TTL emulation and can easily integrate
multiple PAL- and GAL-type devices with densities ranging from 300 to
900 usable gates. The Classic family provides pin-to-pin logic delays as
low as 10 ns and counter frequencies as high as 100 MHz. Classic devices
are available in a wide range of packages, including ceramic dual in-line
package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip
carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA),
and small-outline integrated circuit (SOIC) packages.
EPROM-based Classic devices can reduce active power consumption
without sacrificing performance. This reduced power consumption
makes the Classic family well suited for a wide range of low-power
applications.
Classic devices are 100% generically tested devices in windowed
packages and can be erased with ultra-violet (UV) light, allowing design
changes to be implemented quickly.
Classic devices use sum-of-products logic and a programmable register.
The sum-of-products logic provides a programmable-AND/fixed-OR
structure that can implement logic with up to eight product terms. The
programmable register can be individually programmed for D, T, SR, or
JK flipflop operation or can be bypassed for combinatorial operation. In
addition, macrocell registers can be individually clocked either by a global
clock or by any input or feedback path to the AND array. Altera’s
proprietary programmable I/O architecture allows the designer to
program output and feedback paths for combinatorial or registered
operation in both active-high and active-low modes. These features make
it possible to implement a variety of logic functions simultaneously.
Classic devices are supported by Altera’s MAX+PLUS II development
system, a single, integrated package that offers schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The
MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL,
Verilog HDL, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and workstation-
based EDA tools. The MAX+PLUS II software runs on Windows-based
PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations. These devices also contain on-board logic test
circuitry to allow verification of function and AC specifications during
standard production flow.
746 Altera Corporation


Features May 1999, ver. 5 Features Classic ® EP LD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-vol atile EPROM configuration elements s Fa st pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz s 24 to 68 pins available in du al in-line package (DIP), plastic J-lea d chip carrier (PLCC), pin-grid array ( PGA), and small-outline integrated circ uit (SOIC) packages s Programmable secu rity bit for protection of proprietary designs s 100% generically tested to pr ovide 100% programming yield s Programm able registers providing D, T, JK, and SR flipflops with individual clear and clock controls s Software design suppor t featuring the Altera® MAX+PLUS® II development system on Windows-based PCs , as well as Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 wo rkstations, and third-party development systems s Programming support with Altera’s Master Programming Un.
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