EP910

May 1999, ver. 5 Features Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-volatile EPROM configuration elements s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz s 24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages s Programmable security bit for protection of proprietary designs s 100% generically tested to provide 100% programming yield s Programmable registers providing D, T, JK, and SR flipflops with individual clear and clock controls s Software design support featuring the Altera® MAX+PLUS® II development system on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and third-party development systems s Programming support with Altera’s Master Programming Unit (MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors s Additional design entry and simulation support provided by EDIF, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Table 1. Classic Device Features Feature Usable gates Macrocells Maximum user I/O pins tPD (ns) fCNT (MHz) EP610 ...