May 1999, ver. 5
Features
Classic
® EPLD Family
Data Sheet
s Complete device family with logic densities of 300 to 900 usable gates (see Table 1)
s Device erasure and reprogramming with non-volatile EPROM configuration elements
s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz
s 24 to 68 pins available in dual in-lin...
