EP1K10 Device Datasheet

EP1K10 Datasheet PDF, Equivalent


Part Number

EP1K10

Description

Programmable Logic Device

Manufacture

Altera

Total Page 30 Pages
Datasheet
Download EP1K10 Datasheet


EP1K10
May 2003, ver. 3.4
ACEX 1K
Programmable Logic Device Family
®
Data Sheet
Features...
Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
– Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array
block (EAB)
– Logic array for general logic functions
High density
– 10,000 to 100,000 typical gates (see Table 1)
– Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
Cost-efficient programmable architecture for high-volume
applications
– Cost-optimized process
– Low cost solution for high-performance communications
applications
System-level features
– MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
– Low power consumption
– Bidirectional I/O performance (setup time [tSU] and clock-to-
output delay [tCO]) up to 250 MHz
– Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Extended temperature range
Table 1. ACEXTM 1K Device Features
Feature
Typical gates
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
EP1K10
10,000
56,000
576
3
12,288
136
EP1K30
30,000
119,000
1,728
6
24,576
171
EP1K50
50,000
199,000
2,880
10
40,960
249
EP1K100
100,000
257,000
4,992
12
49,152
333
13
Altera Corporation
DS-ACEX-3.4
1

EP1K10
ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
– -1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2 for 5.0-V operation
– Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
– Operate with a 2.5-V internal supply voltage
– In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
– ClockLockTM and ClockBoostTM options for reduced clock delay,
clock skew, and clock multiplication
– Built-in, low-skew clock distribution trees
– 100% functional testing of all devices; test vectors or scan chains
are not required
– Pull-up on I/O pins before and during configuration
Flexible interconnect
– FastTrack® Interconnect continuous routing structure for fast,
predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
– Tri-state emulation that implements internal tri-state buses
– Up to six global clock signals and four global clear signals
Powerful I/O pins
– Individual tri-state output enable control for each pin
– Open-drain option on each I/O pin
– Programmable output slew-rate control to reduce switching
noise
– Clamp to VCCIO user-selectable on a pin-by-pin basis
– Supports hot-socketing
2 Altera Corporation


Features May 2003, ver. 3.4 ACEX 1K Programmable Logic Device Family ® Data Sheet Fea tures... ■ Programmable logic device s (PLDs), providing low cost system-on- a-programmable-chip (SOPC) integration in a single device – Enhanced embedde d array for implementing megafunctions such as efficient memory and specialize d logic functions – Dual-port capabil ity with up to 16-bit width per embedde d array block (EAB) – Logic array for general logic functions ■ High densi ty – 10,000 to 100,000 typical gates (see Table 1) – Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity ) ■ Cost-efficient programmable archi tecture for high-volume applications Cost-optimized process – Low cost s olution for high-performance communicat ions applications ■ System-level feat ures – MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices – Low power consumption – Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MH.
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