A500K270 Gates Datasheet

A500K270 Datasheet PDF, Equivalent


Part Number

A500K270

Description

System Gates

Manufacture

Actel

Total Page 30 Pages
Datasheet
Download A500K270 Datasheet


A500K270
v3.0
ProASIC500K Family
Features and Benefits
High Capacity
100,000 to 475,000 System Gates
14k to 63k Bits of Two-Port SRAM
106 to 440 User I/Os
Performance
33 MHz PCI 32-bit PCI
Internal System Performance up to 250 MHz
External System Performance up to 100 MHz
Low Power
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient Logic Cells
High Performance Routing Hierarchy
Ultra Fast Local Network
Efficient Long Line Network
High Speed Very Long Line Network
High Performance Global Network
Nonvolatile and Reprogrammable Flash
Technology
Live at Power Up
No Configuration Device Required
Retains Programmed Design During Power-Down/
Power-Up Cycles
I/O
Mixed 2.5V/3.3V Support with Individually-Selectable
Voltage and Slew Rate
3.3V, PCI Compliance (PCI Revision 2.2)
Secure Programming
The Industrys Most Effective Security Key Prevents Read
Back of Programming Bit Stream
Standard FPGA and ASIC Design Flow
Flexibility with Choice of Industry-Standard Front-End
Tools
Efficient Design Through Front-End Timing and Gate
Optimization
ISP Support
In-System Programming (ISP) with Silicon Sculptor and
Flash Pro
SRAMs and FIFOs
Up to 150 MHz Synchronous and Asynchronous Operation
Netlist Generator Ensures Optimal Usage of Embedded
Memory Blocks
Boundary Scan Test
IEEE Std. 1149.1 (JTAG) Compliant
ProASIC Product Profile
Device
Maximum System Gates
Typical Gates
Maximum Flip-Flops
Embedded RAM Bits
Embedded RAM Blocks (256 X 9)
Logic Tiles
Global Routing Resources
Maximum User I/Os
JTAG
PCI
Package (by Pin Count)
PQFP
PBGA
FBGA
A500K050
100,000
43,000
5,376
14k
6
5,376
4
204
Yes
Yes
208
272
144
A500K130
290,000
105,000
12,800
45k
20
12,800
4
306
Yes
Yes
208
272, 456
144, 256
A500K180
370,000
150,000
18,432
54k
24
18,432
4
362
Yes
Yes
208
456
256
A500K270
475,000
215,000
26,880
63k
28
26,880
4
440
Yes
Yes
208
456
256, 676
February 2002
© 2002 Actel Corporation
1

A500K270
ProASIC500K Family
General Description
The ProASIC 500K familys nonvolatile Flash technology
combines the advantages of ASICs with the benefits of
programmable devices. ProASIC 500K devices shorten
time-to-production by enabling designers to create
high-density systems using existing ASIC or FPGA design
flows and tools. ASIC migration is not necessary for any
volume because the family offers cost effective
reprogrammable solutions, ideal for applications in the
networking, telecom, computer, and consumer markets.
The ProASIC 500K family consists of four devices ranging
from 100k to 475k system gates and with up to 63k bits of
embedded two-port memory. These memory blocks include
hardwired FIFO circuitry as well as circuits to generate or
check parity. This minimizes external logic gate count and
complexity while maximizing flexibility and utility.
Process Technology
The ProASIC 500K family achieves its nonvolatile and
reprogrammability through an advanced 0.25µ, four-level
metal LVCMOS process enhanced with Flash technology.
The use of standard CMOS design techniques to implement
logic and control functions results in highly predictable
performance and gate array compatibility.
Ordering Information
A500K130
PQ
208
Application (Ambient Temperature Range)
Blank = Commercial (0 to +70˚ C)
I = Industrial (-40 to +85˚ C)
PP = Pre-production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Package Type
BG = Plastic Ball Grid Array
PQ = Plastic Quad Flat Pack
FG = Fine Ball Grid Array
Part Number
A500K050 = 100,000 Equivalent System Gates
A500K130 = 290,000 Equivalent System Gates
A500K180 = 370,000 Equivalent System Gates
A500K270 = 475,000 Equivalent System Gates
2 v3.0


Features v3.0 ProASIC™ 500K Family Features a nd Benefits High Capacity • 100,000 t o 475,000 System Gates • 14k to 63k B its of Two-Port SRAM • 106 to 440 Use r I/Os Performance • 33 MHz PCI 32-bi t PCI • Internal System Performance u p to 250 MHz • External System Perfor mance up to 100 MHz Low Power • Low I mpedance Flash Switches • Segmented H ierarchical Routing Structure • Small , Efficient Logic Cells High Performanc e Routing Hierarchy • Ultra Fast Loca l Network • Efficient Long Line Netwo rk • High Speed Very Long Line Networ k • High Performance Global Network N onvolatile and Reprogrammable Flash Tec hnology • Live at Power Up • No Con figuration Device Required • Retains Programmed Design During Power-Down/ Po wer-Up Cycles I/O • Mixed 2.5V/3.3V Support with Individually-Selectable Vo ltage and Slew Rate • 3.3V, PCI Compl iance (PCI Revision 2.2) Secure Program ming The Industry’s Most Effective Se curity Key Prevents Read Back of Programming Bit Stream Standard FPGA and ASIC Design Flow • Flexibilit.
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