LTC2000A DACs Datasheet

LTC2000A Datasheet PDF, Equivalent


Part Number

LTC2000A

Description

16-/14-/11-Bit 2.7Gsps DACs

Manufacture

Analog Devices

Total Page 30 Pages
PDF Download
Download LTC2000A Datasheet PDF


LTC2000A
FEATURES
n 80dBc SFDR at 50MHz fOUT
n >68dBc SFDR from DC to 1080MHz fOUT
n 40mA Nominal Full-Scale, ±1V Output Compliant
n 10mA to 60mA Adjustable Full-Scale Current Range
n Single or Dual Port DDR LVDS and DHSTL Interface
n Low Latency (7.5 Cycles for Single Port,
11 Cycles for Dual Port)
n >78dBc 2-Tone IMD from DC to 1000MHz fOUT
n –156dBc/Hz Additive Phase Noise at 1MHz Offset for
65MHz fOUT
n 170-Lead (9mm × 15mm) BGA Package
APPLICATIONS
n Broadband Communication Systems
n DOCSIS CMTS
n Direct RF Synthesis
n Radar
n Instrumentation
n Automatic Test Equipment
LTC2000A
16-/14-/11-Bit 2.7Gsps
DACs
DESCRIPTION
The LTC®2000A is a family of 16-/14-/11-bit 2.7Gsps
current steering DACs with exceptional spectral purity.
The single (1.35Gsps mode) or dual (2.7Gsps mode) port
source synchronous LVDS interface supports data rates of
up to 1.35Gbps using a 675MHz DDR data clock, which
can be either in quadrature or in phase with the data. An
internal synchronizer automatically aligns the data with
the DAC sample clock.
Additional features such as pattern generation, LVDS
loopout and junction temperature sensing simplify system
development and testing.
A serial peripheral interface (SPI) port allows configura-
tion and read back of internal registers. Operating from
1.86V and 3.3V supplies, the LTC2000A consumes 2.41W
at 2.7Gsps and 1.43W at 1.35Gsps.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 8330633.
BLOCK DIAGRAM
TSTP/N
JUNCTION
TEMPERATURE
PATTERN
GENERATOR
PD CS SCK SDI SDO
SPI
SVDD
DAP/N[15:0]
DBP/N[15:0]
4:1 16-BIT DAC
IOUTP
50Ω
50Ω IOUTN
DCKIP/N
DCKOP/N
AVDD18
DELAY
ADJUST
CLK DIVIDER
÷2 OR ÷4
DVDD18
AVDD33
CLOCK
SYNC
DVDD33
GND
GAIN
ADJUST
CLK
RECEIVER
CKP/N
10k
REF
FSADJ
REFIO
2000A BD
For more information www.linear.com/LTC2000A
SFDR vs fOUT, fDAC = 2.7Gsps
100
DIGITAL AMPLITUDE = 0dBFS
IOUTFS = 40mA
90
80
70
60
50
0
200 400 600 800 1000 1200
fOUT (MHz)
2000A TA01b
2000afb
1

LTC2000A
LTC2000A
TABLE OF CONTENTS
Features ..................................................... 1
Applications ................................................ 1
Block Diagram.............................................. 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 3
Pin Configuration .......................................... 3
Order Information.......................................... 4
Electrical Characteristics ................................. 5
Timing Characteristics .................................... 8
Typical Performance Characteristics ................... 9
Pin Functions .............................................. 16
Block Diagram............................................. 17
Timing Diagrams ......................................... 18
Operation................................................... 18
Introduction ............................................................ 18
Dual-Port Mode ...................................................... 19
Single-Port Mode.................................................... 19
Serial Peripheral Interface (SPI) .............................22
Power-On Reset......................................................22
Power Down ...........................................................22
Reference Operation ...............................................22
Setting the Full-Scale Current .................................23
DAC Transfer Function ............................................ 24
Analog Outputs (IOUTP/N)........................................ 24
DAC Sample Clock (CKP/N) ....................................25
Divided Clock Output (DCKOP/N)............................25
LVDS Data Clock Input (DCKIP/N) ..........................25
LVDS Data Input Ports (DAP/N, DBP/N) .................26
Clock Synchronizer ................................................. 27
Minimizing Harmonic Distortion .............................29
Measuring LVDS Input Timing Skew.......................29
Measuring Internal Junction Temperature (TJ) ....... 32
Pattern Generator ................................................... 32
SPI Register Summary................................... 33
Applications Information ................................ 34
Sample Start-Up Sequence.....................................34
Output Configurations ...........................................35
Generating the DAC Sample Clock ..........................35
Synchronizing Multiple LTC2000As in Dual-Port
Mode ......................................................................36
Synchronizing Multiple LTC2000As in Single-Port
Mode ......................................................................38
PCB Layout Considerations ....................................40
Pin Locations (LTC2000A-16) ........................... 45
Pin Locations (LTC2000A-14) ........................... 47
Pin Locations (LTC2000A-11) ........................... 49
Package Description ..................................... 51
Typical Application ....................................... 52
Related Parts .............................................. 52
2000afb
2 For more information www.linear.com/LTC2000A


Features FEATURES n 80dBc SFDR at 50MHz fOUT n >6 8dBc SFDR from DC to 1080MHz fOUT n 40m A Nominal Full-Scale, ±1V Output Compl iant n 10mA to 60mA Adjustable Full-Sca le Current Range n Single or Dual Port DDR LVDS and DHSTL Interface n Low Late ncy (7.5 Cycles for Single Port, 11 Cyc les for Dual Port) n >78dBc 2-Tone IMD from DC to 1000MHz fOUT n –156dBc/Hz Additive Phase Noise at 1MHz Offset for 65MHz fOUT n 170-Lead (9mm × 15mm) BG A Package APPLICATIONS n Broadband Comm unication Systems n DOCSIS CMTS n Direc t RF Synthesis n Radar n Instrumentatio n n Automatic Test Equipment LTC2000A 16-/14-/11-Bit 2.7Gsps DACs DESCRIPTION The LTC®2000A is a family of 16-/14-/ 11-bit 2.7Gsps current steering DACs wi th exceptional spectral purity. The sin gle (1.35Gsps mode) or dual (2.7Gsps mo de) port source synchronous LVDS interf ace supports data rates of up to 1.35Gb ps using a 675MHz DDR data clock, which can be either in quadrature or in phas e with the data. An internal synchronizer automatically aligns the d.
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