74147 ENCODERS Datasheet

74147 Datasheet PDF, Equivalent


Part Number

74147

Description

PRIORITY ENCODERS

Manufacture

Motorola

Total Page 5 Pages
Datasheet
Download 74147 Datasheet


74147
10-LINE-TO-4-LINE
AND 8-LINE-TO-3-LINE
PRIORITY ENCODERS
The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. They
provide priority decoding of the inputs to ensure that only the highest order
data line is encoded. Both devices have data inputs and outputs which are
active at the low logic level.
The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied
decimal zero condition does not require an input condition because zero is
encoded when all nine data lines are at a high logic level.
The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By
providing cascading circuitry (Enable Input EI and Enable Output EO) octal
expansion is allowed without needing external circuitry.
The SN54 / 74LS748 is a proprietary Motorola part incorporating a built-in
deglitcher network which minimizes glitches on the GS output. The glitch
occurs on the negative going transition of the EI input when data inputs 0 – 7
are at logical ones.
The only dc parameter differences between the LS148 and the LS748 are
that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on
the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a
fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148.
The only ac difference is that tPHL from EI to EO is changed from 40 to
45 ns.
SN54 / 74LS147
(TOP VIEW)
OUTPUT
INPUTS
OUTPUT
VCC NC D 3 2 1 9 A
16 15 14 13 12 11 10 9
D 32 1 9
4A
5 678C B
1 2 3 4 56 78
4 5 6 7 8 C B GND
INPUTS
OUTPUTS
SN54 / 74LS148
SN54 / 74LS748
(TOP VIEW)
OUTPUTS
VCC EO GS
16 15 14
3
13
INPUTS
21
12 11
OUTPUT
0 A0
10 9
EO GS 3 2 1 0
4 A0
5 6 7 EI A2 A1
1 2 3 4 56 78
4 5 6 7 E1 A2 A1 GND
INPUTS
OUTPUTS
FAST AND LS TTL DATA
5-1
SN54/74LS147
SN54/74LS148
SN54/74LS748
10-LINE-TO-4-LINE
AND 8-LINE-TO-3-LINE
PRIORITY ENCODERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC

74147
SN54/74LS147 SN54/74LS148 SN54/74LS748
SN54 / 74LS147
FUNCTION TABLE
INPUTS
OUTPUTS
1 2 3 4 5 6 7 8 9 DCBA
HH HHH HHHH HH HH
XX XXX XXXL LHHL
XX X XX XX LH LH HH
XX XXX X L HHHL L L
XX XXX LHHHHL LH
XX XX L HHHHHL HL
XX X LHHHHHHL HH
XX L HHHHHHHH L L
X L HHHHHHHHH LH
L H HHH HH HH HH H L
H = HIGH Logic Level, L = LOW Logic Level, X = Irrelevant
SN54 / 74LS148
SN54 / 74LS748
FUNCTION TABLE
INPUTS
OUTPUTS
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
HX XXXXXXX H H H H H
L H HHHHHHH H H H H L
L X XXXXXXL L L L L H
L X XXXXXLH L L H L H
L X XXXX LHH L H L L H
L X XXX LHHH L H H L H
L X XX LHHHH H L L L H
L X X LHHHHH H L H L H
L X LHHHHHH H H L L H
L L HHHHHHH H H H L H
1 (11)
(12)
2
(13)
3
(1)
4
5 (2)
(3)
6
7 (4)
(5)
8
9 (10)
FUNCTIONAL BLOCK DIAGRAMS
(9) A
(7) B
(6)
C
SN54 / 74LS147
(14) D
(10)
0
(11)
1
(12)
2
(13)
3
4 (1)
(2)
5
(3)
6
(4)
7
(5)
EI
SN54 / 74LS148
(15)
EO
(14)
GS
(8)
A0
(7)
A1
(6)
A2
FAST AND LS TTL DATA
5-2


Features 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE P RIORITY ENCODERS The SN54 / 74LS147 an d the SN54 / 74LS148 are Priority Encod ers. They provide priority decoding of the inputs to ensure that only the high est order data line is encoded. Both de vices have data inputs and outputs whic h are active at the low logic level. Th e LS147 encodes nine data lines to four -line (8-4-2-1) BCD. The implied decima l zero condition does not require an in put condition because zero is encoded w hen all nine data lines are at a high l ogic level. The LS148 encodes eight dat a lines to three-line (4-2-1) binary (o ctal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without nee ding external circuitry. The SN54 / 74L S748 is a proprietary Motorola part inc orporating a built-in deglitcher networ k which minimizes glitches on the GS ou tput. The glitch occurs on the negative going transition of the EI input when data inputs 0 – 7 are at logical ones. The only dc parameter di.
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