71421SA RAM Datasheet

71421SA Datasheet PDF, Equivalent


Part Number

71421SA

Description

HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

Manufacture

IDT

Total Page 18 Pages
PDF Download
Download 71421SA Datasheet PDF


71421SA
HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
71321SA/LA
71421SA/LA
Features
High-speed access
– Commercial: 20/35/55ns (max.)
– Industrial: 25/55ns (max.)
Low-power operation
– IDT71321/IDT71421SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT71321/421LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
Two INT flags for port-to-port communications
MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
On-chip port arbitration logic (IDT71321 only)
BUSY output flag on IDT71321; BUSY input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and
64-Pin STQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A10L
A0L
I/O
Control
I/O
Control
Address
Decoder
11
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
11
CER
OER
R/WR
I/O0R-I/O7R
BUSYR(1,2)
A10R
A0R
INTL(2)
NOTES:
1. IDT71321(MASTER): BUSYisopendrainoutputandrequirespullupresistorof270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
©2019 Integrated Device Technology, Inc.
1
INTR(2)
2691 drw 01
SEPTEMBER 2019
DSC-2691/17

71421SA
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor communications.
The IDT71321 is designed to be used as a stand-alone 8-bit Dual-
Port Static RAM or as a "MASTER" Dual-Port Static RAM together
with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap-
proach in 16-or-more-bit memory system applications results in full
speed, error-free operation without the need for additional discrete
logic.
Both devices provide two independent ports with separate control,
Industrial and Commercial Temperature Ranges
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in 52-pin PLCC,
52-pin STQFP, 64-pin TQFP, and 64-pin STQFP.
Pin Configurations(1,2,3)
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
I/O 0R
I/O 1R
I/O 2R
I/O 3R
I/O 4R
I/O 5R
I/O 6R
20 19 18 17 16 15 14 13 12 11 10 9 8
21 7
22 6
23 5
24 4
25 3
26 2
27
71321/421
1
28 PLG52(4) 52
29 PLCC
Top View
30
51
50
31 49
32 48
33 47
34 35 36 37 38 39 40 41 42 43 44 45 46
A0L
OEL
A10L
INTL
BUSYL
R/WL
CEL
VCC
CER
R/WR
BUSYR
INTR
A10R
2691 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PLG52 package body is approximately .75 in x .75 in x .17 in.
PNG64 package body is approximately 14mm x 14mm x 1.4mm.
PPG64 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
N/C
N/C
A10R
INTR
BUSYR
R/WR
CER
VCC
VCC
CEL
R/WL
BUSYL
INTL
A10L
N/C
N/C
48 4746 45444342 41 40 39 38 3736 3534 33
49 32
50 31
51 30
52 29
53 28
54 27
55
71321/421
26
56
PNG64/PPG64(4)
25
57 24
58
59
64-Pin TQFP
64-Pin STQFP
Top View
23
22
60 21
61 20
62 19
63 18
64 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I/O5R
I/O4R
N/C
I/O3R
I/O2R
I/O1R
I/O0R
GND
GND
N/C
I/O7L
I/O6L
I/O5L
I/O4L
N/C
I/O3L
2691 drw 03
6.242


Features HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM W ITH INTERRUPTS 71321SA/LA 71421SA/LA Features ◆ High-speed access – Comm ercial: 20/35/55ns (max.) – Industria l: 25/55ns (max.) ◆ Low-power operati on – IDT71321/IDT71421SA — Active: 325mW (typ.) — Standby: 5mW (typ.) IDT71321/421LA — Active: 325mW (typ .) — Standby: 1mW (typ.) ◆ Two INT flags for port-to-port communications ◆ MASTER IDT71321 easily expands data bus width to 16-ormore-bits using SLAV E IDT71421 ◆ On-chip port arbitration logic (IDT71321 only) ◆ BUSY output flag on IDT71321; BUSY input on IDT7142 1 ◆ Fully asynchronous operation from either port ◆ Battery backup operati on – 2V data retention (LA only) ◆ TTL-compatible, single 5V ±10% power s upply ◆ Available in 52-Pin PLCC, 52- Pin STQFP, 64-Pin TQFP, and 64-Pin STQF P ◆ Industrial temperature range (– 40°C to +85°C) is available for selec ted speeds ◆ Green parts available, s ee ordering information Functional Block Diagram OEL CEL R/WL OER CER R/WR I/O0L- I/O7L BUSYL(1,2) A10L A0.
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