NTE74LS75 Latch Datasheet

NTE74LS75 Datasheet PDF, Equivalent


Part Number

NTE74LS75

Description

4-Bit Bistable Latch

Manufacture

NTE

Total Page 3 Pages
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NTE74LS75
NTE74LS75
Integrated Circuit
TTL 4Bit Bistable Latch
Description:
The NTE74LS75 is a 4bit bistable latch in a 16Lead plastic DIP type package that is ideally suited
for use as temporary storage for binary information between processing units and input/output or indi-
cator units. Information present at a data (D) input is transferred to the Q output when the enable (C)
is high and the Q output will follow the data input as long as the enable remains high. When the enable
goes low, the information (that was present at the data input at the time the transition occurred) is re-
tained at the Q output until the enable is permitted to go high.
The NTE74LS75 features complementary Q and Q outputs from a 4bit latch and are completely
compatible with all popular TTL families. All inputs are diodeclamped to minimize transmissionline
effects and simplify system design.
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Note 1. Voltage values are with respect to network ground terminal.
Recommended Operating Conditions:
Parameter
Supply Voltage
HighLevel Output Current
LowLevel Output Current
Width of Enabling Pulse
Setup Time
Hold Time
Operating Temperature Range
Symbol
VCC
IOH
IOL
tw
tsu
th
TA
Min Typ Max Unit
4.75 5.0 5.25 V
− − −400 A
− − 8 mA
20
ns
20
ns
5 − − ns
0 +70 C

NTE74LS75
Electrical Characteristics: (Note 2, Note 3)
Parameter
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current
D Input
C Input
High Level Input Current
D Input
C Input
Low Level Input Current
D Input
C Input
ShortCircuit Output Current
Supply Current
Symbol
VIH
VIL
VIK
VOH
VOL
II
IIH
IIL
IOS
ICC
Test Conditions
VCC = MIN, II = 18mA
VCC = MIN, VIH = 2V, VIL = MAX, IOH = -400A
VVCILC==MMAIXN, VIH = 2V,
IOL = 4mA
IOL = 8mA
VCC = MAX, VI = 7V
VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.4V
VCC = MAX, Note 4
VCC = MAX, Note 5
Min Typ Max Unit
2 − −V
− − 0.8 V
− − −1.5 V
2.7 3.5
V
0.25 0.4 V
0.35 0.5 V
− − 0.1 mA
− − 0.4 mA
− − 20 A
− − 80 A
− − −0.4 mA
− − −1.6 mA
20 − −100 mA
6.3 12 mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time, and duration of the shortcircuit
should not exceed one second.
Note 5. ICC is measured with all outputs open and all inputs grounded.
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Propagation Delay Time
(From D input to Q Output)
tPLH
tPHL
RL = 2k, CL = 15pF
15 27 ns
9 17 ns
Propagation Delay Time
(From D input to Q Output)
tPLH
tPHL
12 20 ns
7 15 ns
Propagation Delay Time
(From C input to Q Output)
tPLH
tPHL
15 27 ns
14 25 ns
Propagation Delay Time
(From C input to Q Output)
tPLH
tPHL
16 30 ns
7 15 ns
Function Tables:
Inputs
Outputs
DCQQ
LHLH
HHH L
X L Q0 Q0
H = HIGH Level, L = LOW Level, X = Irrelevant
Q0 = The level of Q before the hightolow transition of G


Features NTE74LS75 Integrated Circuit TTL − 4 Bit Bistable Latch Description: The N TE74LS75 is a 4−bit bistable latch in a 16−Lead plastic DIP type package t hat is ideally suited for use as tempor ary storage for binary information betw een processing units and input/output o r indicator units. Information present at a data (D) input is transferred to t he Q output when the enable (C) is high and the Q output will follow the data input as long as the enable remains hig h. When the enable goes low, the inform ation (that was present at the data inp ut at the time the transition occurred) is retained at the Q output until the enable is permitted to go high. The NTE 74LS75 features complementary Q and Q o utputs from a 4−bit latch and are com pletely compatible with all popular TTL families. All inputs are diode−clamp ed to minimize transmission−line effe cts and simplify system design. Absolu te Maximum Ratings: (Note 1) Supply Vol tage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
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