NTE74LS76A Flip-Flop Datasheet

NTE74LS76A Datasheet PDF, Equivalent


Part Number

NTE74LS76A

Description

Dual J-K Flip-Flop

Manufacture

NTE

Total Page 3 Pages
Datasheet
Download NTE74LS76A Datasheet


NTE74LS76A
NTE74LS76A
Integrated Circuit
TTL Dual JK FlipFlop with Preset and Clear
Description:
The NTE74LS76A is a dual JK flipflop in a 16Lead plastic DIP type package that contains
two independent negativeedgetriggered flipflops. The J and K inputs must be stable one set-
up time prior to the hightolow clock transitions for predictable operation. The preset and clear
are asynchronous active low inputs. When low they override the clock and data inputs forcing
the outputs to the steady state levels as shown in the function table.
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Note 1. Voltage values are with respect to network ground terminal.
Recommended Operating Conditions:
Parameter
Supply Voltage
HighLevel Input Voltage
LowLevel Input Voltage
HighLevel Output Current
LowLevel Output Current
Clock Frequency
Pulse Duration
CLK High
PRE or CLR Low
Setup Time Before CLK
Data High or Low
CLR Inactive
PRE Inactive
Hold Time Data After CLK
Operating Temperature Range
Symbol
VCC
VIH
VIL
IOH
IOL
fclock
tw
tsu
th
TA
Min Typ Max Unit
4.75 5.0 5.25 V
2− −V
− − 0.8 V
− − −0.4 mA
− − 8 mA
0 30 MHz
20
25
ns
ns
20
ns
20
ns
25
ns
0 − − ns
0 +70 C

NTE74LS76A
Electrical Characteristics: (Note 2, Note 3)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current
J or K
VIK VCC = MIN, II = 18mA
VOH VCC = MIN, VIH = 2V, VIL = MAX, IOH = -0.4mA
VOL VVCILC==MMAIXN, VIH = 2V,
IOL = 4mA
IOL = 8mA
II VCC = MAX, VI = 7V
− − −1.5
2.7 3.4
0.25 0.4
0.35 0.5
V
V
V
V
− − 0.1 mA
CLR or PRE
− − 0.3 mA
CLK − − 0.4 mA
High Level Input Current
J or K
IIH VCC = MAX, VI = 2.7V
− − 20 A
CLR or PRE
CLK
Low Level Input Current
J or K
IIL VCC = MAX, VI = 0.4V
− − 60 A
− − 80 A
− − −0.4 mA
All Other
− − −0.8 mA
ShortCircuit Output Current IOS VCC = MAX, Note 4, Note 5
Supply Current
ICC VCC = MAX, Note 6
20 − −100 mA
4 6 mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time, and duration of the shortcircuit
should not exceed one second.
Note 5. For certain devices where state commutation can be caused by shorting an output to ground,
an equivalent test may
reduced to one half of
tbheeipr esrtfaotremdevdawluieths.VO
=
2.125Vand
the
minimum
an
maximum
limits
Note 6. Wmeitahsaulrleomutepnutt,sthoepecnlo, cICkCinipsumt eisagsuroreudndweidth. the Q and Q outputs high in turn. At the time of
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Maximum Clock Frequency
fmax RL = 2k, CL = 15pF
20 45
MHz
Propagation Delay Time
(From PRE, CLR or CLK input to Any Q Output)
tPLH
tPHL
15 20 ns
15 20 ns
Function Tables:
Inputs
Outputs
PRE
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
H
J
X
X
X
L
H
L
H
X
KQQ
XHL
XLH
X H{ H{
L Q0 Q0
LHL
HLH
H Toggle
X Q0 Q0
{ This configuration is nonstable; that is, it will not persist
when wither preset or clear returns to its inactive (high) level.


Features NTE74LS76A Integrated Circuit TTL − Du al J−K Flip−Flop with Preset and Cl ear Description: The NTE74LS76A is a d ual J−K flip−flop in a 16−Lead pl astic DIP type package that contains tw o independent negative−edge−trigger ed flip−flops. The J and K inputs mus t be stable one setup time prior to the high−to−low clock transitions for predictable operation. The preset and c lear are asynchronous active low inputs . When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the fun ction table. Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keywords NTE74LS76A, datasheet, pdf, NTE, Dual, J-K, Flip-Flop, TE74LS76A, E74LS76A, 74LS76A, NTE74LS76, NTE74LS7, NTE74LS, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)