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NTE74LS78 Flip-Flop Datasheet |
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| Part Number | NTE74LS78 |
| Description | Dual J-K Flip-Flop |
| Manufacture | NTE |
| Total Page | 3 Pages |
| PDF Download |
NTE74LS78
Integrated Circuit
TTL − Dual J−K Flip−Flop with Preset,
Common Clock and Common Clear
Description:
The NTE74LS78 is a dual J−K flip−flop in a 14−Lead plastic DIP type package that contains two
negative−edge−triggered flip−flops with individual J−K, preset inputs, and common clock and
common clear inputs. The logic levels at the J and K inputs may be allowed to change while the
clock pulse is high and the flip−flop will perform according to the function table as long as minimum
setup and hold times are observed. The preset and clear are asynchronous active low inputs.
When low they override the clock and data inputs forcing the outputs to the steady state levels as
shown in the function table.
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Note 1. Voltage values are with respect to network ground terminal.
Recommended Operating Conditions:
Parameter
Supply Voltage
High−Level Input Voltage
Low−Level Input Voltage
High−Level Output Current
Low−Level Output Current
Clock Frequency
Pulse Duration
CLK High
PRE or CLR Low
Setup Time Before CLK
Data High or Low
PRE or CLR Inactive
Hold Time Data After CLK
Operating Temperature Range
Symbol
VCC
VIH
VIL
IOH
IOL
fclock
tw
tsu
th
TA
Min Typ Max Unit
4.75 5.0 5.25 V
2− −V
− − 0.8 V
− − −0.4 mA
− − 8 mA
0 − 30 MHz
20 −
25 −
− ns
− ns
20 −
− ns
20 −
− ns
0 − − ns
0 − +70 C
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Electrical Characteristics: (Note 2, Note 3)
Parameter
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current
J or K
CLR
PRE
CLK
High Level Input Current
J or K
CLR
PRE
CLK
Low Level Input Current
J or K
CLR or CLK
PRE
Short−Circuit Output Current
Supply Current
Symbol
VIK
VOH
VOL
II
IIH
IIL
IOS
ICC
Test Conditions
VCC = MIN, II = −18mA
VCC = MIN, VIH = 2V, VIL = 0.8V, IOH = -0.4mA
VVCILC==MMAIXN, VIH = 2V,
IOL = 4mA
IOL = 8mA
VCC = MAX, VI = 7V
VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.4V
VCC = MAX, Note 4, Note 5
VCC = MAX, Note 6
Min Typ Max Unit
− − −1.5 V
2.7 3.4
V
− 0.25 0.4 V
− 0.35 0.5 V
− − 0.1 mA
− − 0.6 mA
− − 0.3 mA
− − 0.8 mA
− − 20 A
− − 120 A
− − 60 A
− − 160 A
− − −0.4 mA
− − −1.6 mA
− − −0.8 mA
−20 − −100 mA
− 4 6 mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time, and duration of the short−circuit
should not exceed one second.
Note 5. For certain devices where state commutation can be caused by shorting an output to ground,
an equivalent test may
reduced to one half of
tbheeipr esrtfaotremdevdawluieths.VO
=
2.125Vand
the
minimum
an
maximum
limits
Note 6. Wmeitahsaulrleomutepnutt,sthoepecnlo, cICkCinipsumt eisagsuroreudndweidth. the Q and Q outputs high in turn. At the time of
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Symbol Test Conditions Min Typ Max Unit
Maximum Clock Frequency
fmax RL = 2k, CL = 15pF 30 45
− MHz
Propagation Delay Time
(From PRE, CLR or CLK input to Any Q Output)
tPLH, tPHL
− 15 20 ns
Function Tables:
Inputs
Outputs
PRE
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
H
J
X
X
X
L
H
L
H
X
KQQ
XHL
XLH
X H{ H{
L Q0 Q0
LHL
HLH
H Toggle
X Q0 Q0
{ This configuration is nonstable; that is, it will not persist
when wither preset or clear returns to its inactive (high) level.
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| Features | NTE74LS78 Integrated Circuit TTL − Dua l J−K Flip−Flop with Preset, Common Clock and Common Clear Description: T he NTE74LS78 is a dual J−K flip−flo p in a 14−Lead plastic DIP type packa ge that contains two negative−edge− triggered flip−flops with individual J−K, preset inputs, and common clock and common clear inputs. The logic leve ls at the J and K inputs may be allowed to change while the clock pulse is hig h and the flip−flop will perform acco rding to the function table as long as minimum setup and hold times are observ ed. The preset and clear are asynchrono us active low inputs. When low they ove rride the clock and data inputs forcing the outputs to the steady state levels as shown in the function table. Absol ute Maximum Ratings: (Note 1) Supply Vo ltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. |
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