NTE74LS74A Flip-Flop Datasheet

NTE74LS74A Datasheet PDF, Equivalent


Part Number

NTE74LS74A

Description

Dual D-Type Positive-Edge-Triggered Flip-Flop

Manufacture

NTE

Total Page 3 Pages
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NTE74LS74A
NTE74LS74A
Integrated Circuit
TTL, Dual DType PositiveEdgeTriggered
FlipFlop w/Preset and Clear
Description:
The NTE74LS74A contains two independent Dtype positiveedgetriggered flipflops in a 14Lead
DIP type package characterized for operating from 0to +70C. A low level at the preset or clear in-
puts sets or resets the outputs regardless of the levels of the other inputs. When preset and clear
are inactive (high), data at the D input meeting the setup time requirements are transferred to the out-
puts on the positivegoing edge of the clock pulse. Clock triggering occurs at a voltage level and is
not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D
input may be changed without affecting the levels at the outputs.
Absolute Maximum Ratings: (TA = 0to +70C unless otherwise specified)
Supply Voltage (Note 1), VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65to +150C
Note 1. Voltage values are with respect to network GND terminal.
Recommended Operating Conditions:
Parameter
Symbol
Supply Voltage
HighLevel Input Voltage
LowLevel Input Voltage
HighLevel Output Current
LowLevel Output Current
Clock Frequency
Pulse Duration
CLK High
VCC
VIH
VIL
IOH
IOL
fclock
tw
PRE or CLR Low
Setup Time Before CLK
Hold TimeData After CLK
Operating Ambient Temperature
tsu
th
TA
Test Conditions
Min Typ Max Unit
4.75 5.0 5.25 V
2 − −V
− − 0.8 V
− − −0.4 mA
− − 8 mA
0 25 MHz
25 − − ns
25 − − ns
20 − − ns
5 − − ns
0 70 C

NTE74LS74A
Electrical Characteristics: (Note 2, Note 3)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Input Clamp Diode Voltage
Output High Voltage
Output Low Voltage
Input Current
D or CLK
VIK VCC = Min, II1 = 12mA
− − −1.5 V
VOH VCC = Min, VIH = 2V, VIL = MAX, IOH = -0.4mA 2.7 3.4
V
VOL VCC = Min, VIH = 2V,
VIL = MAX
IOL = 4mA
IOL = 8mA
0.25 0.4
0.35 0.5
V
V
II VCC = Max, VI = 7V
− − 0.1 mA
CLR or PRE
− − 0.2 mA
Input High Current
D or CLK
IIH VCC = Max, VI = 2.7V
− − 20 A
CLR or PRE
− − 40 A
Input Low Current
D or CLK
IIL VCC = Max, VI = 0.4V
− − −0.4 mA
CLR or PRE
− − −0.8 mA
Output Short Circuit Current
Power Supply Current
IOS VCC = Max, Note 4, Note 5
ICC VCC = Max, Note 6
20 − −100 mA
4 8 mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time, and the duration of the short circuit
should not exceed one second.
Note 5. For certain devices where state commutation can be caused by shorting an output to ground,
an
its
equivalent
reduced to
test may
one half
be
of
tpheerifrosrmtaeteddwviathluVeOs.=
2.125V
with
the
minimum
and
maximum
lim-
Note 6. Wmeitahsaulrleomutepnutt,sthoepecnlo, cICkCinipsumt eisagsuroreudndweidth. the Q and Q outputs high in turn. At the time of
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Maximum Clock Frequency
fmax RL = 2k, CL = 15pF 25 33 MHz
Propagation Delay Time
(From CLR, PRE, or CLK Input to Q or Q Output)
tPLH
tPHL
13 25 ns
25 40 ns
Function Table:
Inputs
Outputs
PRE
CLR
CLK
D
Q
Q
LHXXHL
HL XX L H
L L X X H (Note 6) H (Note 6)
HH HH L
HH L L H
H H L X Q0 Q0
Note
6.
The output
if the lows
nonstable;
alethtvapetrlseissi,neittthwaisnilldcnoconltefipagrruerasaritesiot nnweahareernVneoILitthmgeuaraxpriamrenusteemet.dortFoculmretahereetrremthtuoerrnems, intthoimisituscmoinnlaeficvgteuivlsreaitn(ihoVingOhiHs)
level.


Features NTE74LS74A Integrated Circuit TTL, Dual D−Type Positive−Edge−Triggered Fl ip−Flop w/Preset and Clear Descripti on: The NTE74LS74A contains two indepen dent D−type positive−edge−trigger ed flip−flops in a 14−Lead DIP type package characterized for operating fr om 0 to +70C. A low level at the preset or clear inputs sets or resets t he outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D inp ut meeting the setup time requirements are transferred to the outputs on the p ositive−going edge of the clock pulse . Clock triggering occurs at a voltage level and is not directly related to th e rise time of the clock pulse. Followi ng the hold time interval, data at the D input may be changed without affectin g the levels at the outputs. Absolute Maximum Ratings: (TA = 0 to +70C unless otherwise specified) Supply Volt age (Note 1), VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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