70V35L RAM Datasheet

70V35L Datasheet PDF, Equivalent


Part Number

70V35L

Description

HIGH-SPEED 3.3V STATIC RAM

Manufacture

IDT

Total Page 25 Pages
Datasheet
Download 70V35L Datasheet


70V35L
HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
70V35/34S/L
70V25/24S/L
Features
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70V35
– Commercial: 15ns (max.)
– Industrial: 20ns
IDT70V34
– Commercial: 15ns (max.)
IDT70V25
– Commercial: 15/35ns (max.)
– Industrial: 20/25ns
IDT70V24
– Commercial: 15//35/55ns (max.)
– Industrial: 15/20ns
Low-power operation
– IDT70V35/34L
Active: 415mW (typ.)
Standby: 660μW (typ.)
Functional Block Diagram
R/WL
UBL
– IDT70V25/24S
– IDT70V25/24L
Active: 400mW (typ.)
Active: 380mW (typ.)
Standby: 3.3mW (typ.)
Standby: 660μW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/34) & (IDT70V25/24),
and 84-pin PLCC (IDT70V24)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
R/WR
UBR
LBL
CEL
OEL
I/O9L-I/O17L(5)
I/O0L-I/O8L(4)
BUSYL(2,3)
I/O
Control
I/O
Control
A12L(1)
A0L
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
13
SEML
NOTES:
INTL(3)
1. A12 is a NC for IDT70V34 and for IDT70V24.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
4. I/O0x - I/O7x for IDT70V25/24.
5. I/O8x - I/O15x for IDT70V25/24.
©2019 Integrated Device Technology, Inc.
M/S
1
Address
Decoder
CER
OER
R/WR
LBR
CER
OER
,
I/O9R-I/O17R(5)
I/O0R-I/O8R(4)
BUSYR(2,3)
A12R(1)
A0R
SEMR
INTR(3)
5624 drw 01
OCTOBER 2019
DSC-5624/10

70V35L
70V35/34S/L (70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Description
The IDT70V35/34 (IDT70V25/24) is a high-speed 8/4K x 18 (8/4K
x16) Dual-Port Static RAM. The IDT70V35/34 (IDT70V25/24) is de-
signed to be used as a stand-alone Dual-Port RAM or as a combination
MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
Industrial and Commercial Temperature Ranges
featurecontrolledby CE permitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 430mW (IDT70V35/34) and 400mW
(IDT70V25/24) of power.
The IDT70V35/34 (IDT70V25/24) is packaged in a plastic 100-pin
Thin Quad Flatpack. The IDT70V24 is packaged in a 84-Pin PLCC.
Pin Configurations(1,2,3,4)
A6L
A7L
A8L
A9L
A10L
A11L
A12L(1)
LBL
UBL
CEL
SEML
R/WL
VDD
OEL
I/O0L
I/O1L
Vss
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
I/O9L
I/O10L
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76 50
77 49
78 48
79 47
80 46
81 45
82 44
83 43
84 42
85 41
86 40
87
88
70V35/34
PNG100(5)
39
38
89 100-Pin TQFP
90 Top View
91
37
36
35
92 34
93 33
94 32
95 31
96 30
97 29
98 28
99 27
100 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A5R
A6R
A7R
A8R
A9R
A10R
A11R
A12R(1)
LBR
UBR
CER
SEMR
Vss
R/WR
OER
I/O16R
Vss
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O9R
I/O7R
5624 drw 02
NOTES:
1. A12 is a NC for IDT70V34.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. PNG100 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6.422


Features HIGH-SPEED 3.3V 8/4K x 18 DUAL-PORT 8/4K x 16 DUAL-PORT STATIC RAM 70V35/34S/L 70V25/24S/L Features ◆ True Dual-Po rted memory cells which allow simultane ous reads of the same memory location High-speed access IDT70V35 – Comme rcial: 15ns (max.) – Industrial: 20ns IDT70V34 – Commercial: 15ns (max.) I DT70V25 – Commercial: 15/35ns (max.) – Industrial: 20/25ns IDT70V24 – Co mmercial: 15//35/55ns (max.) – Indust rial: 15/20ns ◆ Low-power operation IDT70V35/34L Active: 415mW (typ.) St andby: 660μW (typ.) Functional Block D iagram R/WL UBL – IDT70V25/24S – IDT70V25/24L Active: 400mW (typ.) Act ive: 380mW (typ.) Standby: 3.3mW (typ. ) Standby: 660μW (typ.) ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ IDT 70V35/34 (IDT70V25/24) easily expands d ata bus width to 36 bits (32 bits) or more using the Master/Slave select whe n cascading more than one device ◆ M /S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆ BUSY and Interrupt .
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