LMX2572 synthesizer Datasheet

LMX2572 Datasheet PDF, Equivalent


Part Number

LMX2572

Description

6.4-GHz Low power wideband RF synthesizer

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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LMX2572
SNAS740B – OCTOBER 2017 – REVISED JANUARY 2019
LMX2572 6.4-GHz Low power wideband RF synthesizer with phase synchronization and
JESD204B support
1 Features
1 Output frequency: 12.5 MHz to 6.4 GHz
• Low power consumption: 75 mA at 3.3-V supply
• –106-dBc/Hz Phase noise at 100-kHz offset with
6.4-GHz carrier
• PLL figure of merit: –232 dBc/Hz
• PLL normalized 1/f noise: –123.5 dBc/Hz
• 32-Bit Fractional-N divider
• Remove integer boundary spurs with
programmable input multiplier
• Synchronization of output phase across multiple
devices
• Support for JESD204B SYSREF with
programmable delay
• Support for ramp and chirp functions
• Support for FSK direct digital modulation
• Two programmable output power level differential
outputs
• Fast VCO calibration speed: < 20 µs
• Single 3-V to 3.5-V power supply
2 Applications
• Test and measurement equipment
• Digital 2-way radios
• Low power radio communication systems
• Satellite communication
• Wireless microphones
• Propriety wireless connectivity
• MIMO
• RADAR
• High-speed data converter clocking
3 Description
The LMX2572 is a low-power, high-performance
wideband synthesizer that can generate any
frequency from 12.5 MHz to 6.4 GHz without using an
internal doubler. The PLL delivers excellent
performance while consuming just 75 mA from a
single 3.3-V supply.
For applications like digital mobile radio (DMR) and
wireless microphones, the LMX2572 supports FSK
modulation. Discrete level FSK and pulse-shaping
FSK are supported. Direct digital FSK modulation is
achievable through programming or pins.
The LMX2572 allows users to synchronize the output
of multiple devices and also enables applications that
need deterministic delay between input and output.
The LMX2572 provides an option to adjust the phase
with fine granularity to account for delay mismatch on
the board or within devices. A frequency ramp
generator can synthesize up to two segments of ramp
in an automatic ramp generation option or a manual
option for maximum flexibility. The fast calibration
algorithm allows the user to change frequencies
faster than 20 µs. The LMX2572 also supports
generating or repeating SYSREF (compliant to
JESD204B standard) making it an ideal low-power,
low-noise clock source for clocking high-speed data
converters. Fine delay adjustment is provided in this
configuration to account for delay differences of board
traces.
The LMX2572 integrates LDOs from a single 3.3-V
supply, thus eliminating the need for onboard low-
noise LDOs.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMX2572
VQFN (40)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
CPout Vtune
OSCinP
OSCinM
CSB
SCK
SDI
MUXout
x2
Serial Interface
Pre-R
Divider
MULT
LDOs
Lock Detect or
Register Readback
Phase
Sync
Enable
Post-R
Divider
, Charge
Pump
N-Divider
Ramp Generator
FSK Generator
û
Modulator
÷2/4/8«/256
SYSREF
RFoutAP
RFoutAM
RFoutBP
RFoutBM
SYNC
CE RampClk RampDir
SysRefReq
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMX2572
LMX2572
SNAS740B – OCTOBER 2017 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information .................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements ................................................ 8
6.7 Timing Diagrams ....................................................... 9
6.8 Typical Characteristics ............................................ 10
7 Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 20
7.5 Programming........................................................... 21
7.6 Register Maps ......................................................... 24
8 Application and Implementation ........................ 64
8.1 Application Information............................................ 64
8.2 Typical Application .................................................. 76
8.3 Do's and Don'ts ....................................................... 78
9 Power Supply Recommendations...................... 79
10 Layout................................................................... 80
10.1 Layout Guidelines ................................................. 80
10.2 Layout Example .................................................... 80
11 Device and Documentation Support ................. 81
11.1 Device Support...................................................... 81
11.2 Documentation Support ........................................ 81
11.3 Receiving Notification of Documentation Updates 81
11.4 Community Resources.......................................... 81
11.5 Trademarks ........................................................... 81
11.6 Electrostatic Discharge Caution ............................ 81
11.7 Glossary ................................................................ 81
12 Mechanical, Packaging, and Orderable
Information ........................................................... 81
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2017) to Revision B
Page
• Changed RampDir pin description from: …ramp size selection… to: …ramp segment selection… ..................................... 4
• Changed RFoutAM pin description from: High impedance… to: Low impedance….............................................................. 4
• Changed RFoutAP pin description from: High impedance… to: Low impedance… .............................................................. 4
• Changed RFoutBM pin description from: High impedance… to: Low impedance….............................................................. 4
• Changed RFoutBP pin description from: High impedance… to: Low impedance… .............................................................. 4
• Changed VbiasVCO pin decoupling capacitor requirement ................................................................................................... 5
• Changed VbiasVCO2 pin decoupling capacitor requirement ................................................................................................. 5
• Changed VccMASH pin decoupling capacitor requirement ................................................................................................... 5
• Changed VccVCO pin decoupling capacitor requirement ...................................................................................................... 5
• Changed VccVCO2 pin decoupling capacitor requirement .................................................................................................... 5
• Changed VregVCO pin decoupling capacitor requirement .................................................................................................... 5
• Added Vtune pin shunt capacitor requirement ....................................................................................................................... 5
• Changed VOH and VOL data in Electrical Characteristics ........................................................................................................ 8
• Changed SCK to CSB low time symbol ................................................................................................................................ 8
• Changed Figure 28............................................................................................................................................................... 13
• Added charge pump gain table............................................................................................................................................. 16
• Deleted sentence 'When the device comes out of the powered down state, either by resuming the POWERDOWN
bit to zero or by pulling back CE pin HIGH (if it was powered down by CE pin), it is required that register R0 with
FCAL_EN = 1 be programmed again to re-calibrate the device.' from the Powerdown section.......................................... 18
• Added sentence 'The wake-up time for the device to come out of the powered state is adjustable.' to the
Powerdown section............................................................................................................................................................... 18
• Changed Programming Sequence step from: Wait 100 µs… to: Wait 500 µs… ................................................................. 21
• Changed R6 initial programming from: No to: Depends....................................................................................................... 21
• Changed R52 initial programming from: No to: Yes............................................................................................................. 22
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Product Folder Links: LMX2572
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Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity LMX2572 SNAS740B – OCTOBER 20 17 – REVISED JANUARY 2019 LMX2572 6.4 -GHz Low power wideband RF synthesizer with phase synchronization and JESD204B support 1 Features •1 Output freque ncy: 12.5 MHz to 6.4 GHz • Low power consumption: 75 mA at 3.3-V supply • –106-dBc/Hz Phase noise at 100-kHz of fset with 6.4-GHz carrier • PLL figur e of merit: –232 dBc/Hz • PLL norma lized 1/f noise: –123.5 dBc/Hz • 32 -Bit Fractional-N divider • Remove in teger boundary spurs with programmable input multiplier • Synchronization of output phase across multiple devices Support for JESD204B SYSREF with pro grammable delay • Support for ramp an d chirp functions • Support for FSK d irect digital modulation • Two progra mmable output power level differential outputs • Fast VCO calibration speed: < 20 µs • Single 3-V to 3.5-V power supply 2 Applications • Test and measurement equipment • Digital 2-way radios • Low power radio commu.
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