LMX2594 Synthesizer Datasheet

LMX2594 Datasheet PDF, Equivalent


Part Number

LMX2594

Description

RF Synthesizer

Manufacture

etcTI

Total Page 30 Pages
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LMX2594
SNAS696C – MARCH 2017 – REVISED APRIL 2019
LMX2594 15-GHz Wideband PLLATINUM™ RF Synthesizer
With Phase Synchronization and JESD204B Support
1 Features
1 10-MHz to 15-GHz output frequency
• –110 dBc/Hz phase noise at 100-kHz offset with
15-GHz carrier
• 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
• Programmable output power
• PLL key specifications
– Figure of merit: –236 dBc/Hz
– Normalized 1/f noise: –129 dBc/Hz
– High phase detector frequency
– 400-MHz integer mode
– 300-MHz fractional mode
– 32-bit fractional-N divider
• Remove integer boundary spurs with
programmable input multiplier
• Synchronization of output phase across multiple
devices
• Support for SYSREF with 9-ps resolution
programmable delay
• Frequency ramp and chirp generation ability for
FMCW applications
• < 20-µs VCO calibration speed
• 3.3-V single power supply operation
2 Applications
• 5G and mm-Wave wireless infrastructure
• Test and measurement equipment
• Radar
• MIMO
• Phased array antennas and beam forming
• High-speed data converter clocking (supports
JESD204B)
3 Description
The LMX2594 is a high-performance, wideband
synthesizer that can generate any frequency from 10
MHz to 15 GHz without using an internal doubler,
thus eliminating the need for sub-harmonic filters. The
high-performance PLL with figure of merit of –236
dBc/Hz and high-phase detector frequency can attain
very low in-band noise and integrated jitter. The high-
speed N-divider has no pre-divider, thus significantly
reducing the amplitude and number of spurs. There is
also a programmable input multiplier to mitigate
integer boundary spurs.
The LMX2594 allows users to synchronize the output
of multiple devices and also enables applications that
need deterministic delay between input and output. A
frequency ramp generator can synthesize up to two
segments of ramp in an automatic ramp generation
option or a manual option for maximum flexibility. The
fast calibration algorithm allows changing frequencies
faster than 20 µs. The LMX2594 adds support for
generating or repeating SYSREF (compliant to
JESD204B standard) designed for low-noise clock
sources in high-speed data converters. A fine delay
adjustment (9-ps resolution) is provided in this
configuration to account for delay differences of board
traces.
The output drivers within LMX2594 deliver output
power as high as 7 dBm at 15-GHz carrier frequency.
The device runs from a single 3.3-V supply and has
integrated LDOs that eliminate the need for on-board
low noise LDOs.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMX2594
VQFN (40)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Input
signal
OSCinP
OSCinM
CSB
SCK
SDI
MUXout
Simplified Schematic
OSCin
Douber
Pre-R
Divider
Multiplier
Post-R
Divider
Phase
Detector
ϕ
Charge
Pump
Serial Interface
Control
Sigma-Delta
Modulator
N Divider
Channel
Divider
SYSREF
MUX
MUX
CPout Loop Filter
Vtune
RFoutAP
Vcc
RFoutAM
RFoutBM
Vcc
RFoutBP
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMX2594
LMX2594
SNAS696C – MARCH 2017 – REVISED APRIL 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 6
6 Specifications......................................................... 8
6.1 Absolute Maximum Ratings ...................................... 8
6.2 ESD Ratings.............................................................. 8
6.3 Recommended Operating Conditions....................... 8
6.4 Thermal Information .................................................. 8
6.5 Electrical Characteristics........................................... 9
6.6 Timing Requirements .............................................. 11
6.7 Typical Characteristics ............................................ 14
7 Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 39
7.5 Programming........................................................... 40
7.6 Register Maps ......................................................... 41
8 Application and Implementation ........................ 59
8.1 Application Information............................................ 59
8.2 Typical Application .................................................. 61
9 Power Supply Recommendations...................... 64
10 Layout................................................................... 65
10.1 Layout Guidelines ................................................. 65
10.2 Layout Example .................................................... 66
11 Device and Documentation Support ................. 67
11.1 Device Support...................................................... 67
11.2 Documentation Support ........................................ 67
11.3 Receiving Notification of Documentation Updates 67
11.4 Community Resources.......................................... 67
11.5 Trademarks ........................................................... 67
11.6 Electrostatic Discharge Caution ............................ 67
11.7 Glossary ................................................................ 67
12 Mechanical, Packaging, and Orderable
Information ........................................................... 68
4 Revision History
Changes from Revision B (March 2018) to Revision C
Page
• Deleted the recommended bypass capacitor values for Vcc pins 7, 11, 15, 21, 26 and 37, as these capacitor values
are not mandatory and the power supply filtering design is up to the user............................................................................ 7
• Changed all the 'FRAC_ORDER' to 'MASH_ORDER' to avoid confusion ............................................................................. 9
• Changed the names of timing specs to align with timing diagram: changed tCE to tES, tCS to tDCS, tCH to tCDH, and tCES
to tECS.................................................................................................................................................................................... 11
• Changed the names of timing specs to align with timing diagram: changed tES to tCE, tCES to tECS, added tDCS and
tCDH, and changed tCS to tCR.................................................................................................................................................. 12
• Changed the serial data input timing diagram and corrected the typo for 'SCK'.................................................................. 12
• Deleted the note 'The CSB transition from high to low must occur when SCK is low' from the serial data input timing
diagram, because SPI mode 4 (CPOL = 1, CPHA = 1) is also supported, and SCK is held high when idle in mode 4 ..... 12
• Added note for the serial data input timing diagram to explain the tCE requirement for mode 4 (CPOL = 1, CPHA = 1)
of SPI, because the diagram only indicated SPI mode 1 (CPOL = 0, CPHA = 0) ............................................................... 12
• Changed the serial data readback timing diagram............................................................................................................... 13
• Changed the note about MUXout clocking out and emphasized the effect of tCR on the readback data available time ..... 13
• Changed the fOUT test conditions in the Closed-Loop Phase Noise at 3.5 GHz graph from: 14 GHz / 2 = 3.5 GHz to:
to 14 GHz / 4 = 3.5 GHz ...................................................................................................................................................... 15
• Added Normalized Output Power Across OUTA_PWR With Resistor Pullup graph............................................................ 15
• Changed "Vtune" to "Indirect Vtune" when LD_TYPE = 1 ................................................................................................... 21
• Changed description for LD_TYPE. .................................................................................................................................... 21
• Added description of Indirect Vtune. ................................................................................................................................... 22
• Added description for the 'no assist' mode, mphasized the effect of VCO_SEL, VCO_DACISET_STRT and
VCO_CAPCTRL_STRT under 'no assist' mode, and added recommended values for these registers .............................. 23
• Added description for the 'full assist' mode to allow the user to set VCO amplitude and capcode using linear
interpolation under certain conditions................................................................................................................................... 23
• Changed OUTx_PWR Recommendations for Resistor Pullup table ................................................................................... 25
• Added description for category 3 of SYNC feature stating that FCAL_EN needs to be 1. .................................................. 29
• Changed description of MASH_SEED ................................................................................................................................ 29
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Product Folder Links: LMX2594
Copyright © 2017–2019, Texas Instruments Incorporated


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity LMX2594 SNAS696C – MARCH 2017 – REVISED APRIL 2019 LMX2594 15-GHz Wideband PLLATINUM™ RF Synthesizer Wi th Phase Synchronization and JESD204B S upport 1 Features •1 10-MHz to 15-GH z output frequency • –110 dBc/Hz ph ase noise at 100-kHz offset with 15-GHz carrier • 45-fs rms jitter at 7.5 GH z (100 Hz to 100 MHz) • Programmable output power • PLL key specifications – Figure of merit: –236 dBc/Hz – Normalized 1/f noise: –129 dBc/Hz High phase detector frequency – 400 -MHz integer mode – 300-MHz fractiona l mode – 32-bit fractional-N divider • Remove integer boundary spurs with programmable input multiplier • Synch ronization of output phase across multi ple devices • Support for SYSREF with 9-ps resolution programmable delay • Frequency ramp and chirp generation ab ility for FMCW applications • < 20-µ s VCO calibration speed • 3.3-V single power supply operation 2 Applications • 5G and mm-Wave wireless infra.
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