LMX2595 Synthesizer Datasheet

LMX2595 Datasheet PDF, Equivalent


Part Number

LMX2595

Description

RF Synthesizer

Manufacture

etcTI

Total Page 30 Pages
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LMX2595
SNAS736C – JUNE 2017 – REVISED APRIL 2019
LMX2595 20-GHz Wideband PLLATINUM™ RF Synthesizer
With Phase Synchronization and JESD204B Support
1 Features
1 10-MHz to 20-GHz output frequency
• –110 dBc/Hz phase noise at 100-kHz offset with
15-GHz carrier
• 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
• Programmable output power
• PLL key specifications
– Figure of merit: –236 dBc/Hz
– Normalized 1/f noise: –129 dBc/Hz
– High phase detector frequency
– 400-MHz integer mode
– 300-MHz fractional mode
– 32-bit fractional-N divider
• Remove integer boundary spurs with
programmable input multiplier
• Synchronization of output phase across multiple
devices
• Support for SYSREF with 9-ps resolution
programmable delay
• Frequency ramp and chirp generation ability for
FMCW applications
• < 20-µs VCO calibration speed
• 3.3-V single power supply operation
2 Applications
• 5G and mm-Wave wireless infrastructure
• Test and measurement equipment
• Radar
• MIMO
• Phased array antennas and beam forming
• High-speed data converter clocking (supports
JESD204B)
3 Description
The LMX2595 high-performance, wideband
synthesizer that can generate any frequency from 10
MHz to 20 GHz. An integrated doubler is used for
frequencies above 15 GHz. The high-performance
PLL with figure of merit of –236 dBc/Hz and high-
phase detector frequency can attain very low in-band
noise and integrated jitter. The high-speed N-divider
has no pre-divider, thus significantly reducing the
amplitude and number of spurs. There is also a
programmable input multiplier to mitigate integer
boundary spurs.
The LMX2595 allows users to synchronize the output
of multiple devices and also enables applications that
need deterministic delay between input and output. A
frequency ramp generator can synthesize up to two
segments of ramp in an automatic ramp generation
option or a manual option for maximum flexibility. The
fast calibration algorithm allows changing frequencies
faster than 20 µs. The LMX2595 adds support for
generating or repeating SYSREF (compliant to
JESD204B standard) designed for low-noise clock
sources in high-speed data converters. A fine delay
adjustment (9-ps resolution) is provided in this
configuration to account for delay differences of board
traces.
The output drivers within LMX2595 deliver output
power as high as 7 dBm at 15-GHz carrier frequency.
The device runs from a single 3.3-V supply and has
integrated LDOs that eliminate the need for on-board
low noise LDOs.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMX2595
VQFN (40)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Input
signal
OSCinP
OSCinM
CSB
SCK
SDI
MUXout
Simplified Schematic
OSCin
Douber
Pre-R
Divider
Multiplier
Post-R
Divider
Phase
Detector
I
Charge
Pump
Serial Interface
Control
Sigma-Delta
Modulator
N Divider
2X
Channel
Divider
SYSREF
MUX
MUX
Loop Filter
CPout
Vtune
RFoutAP
Vcc
RFoutAM
RFoutBM
Vcc
RFoutBP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMX2595
LMX2595
SNAS736C – JUNE 2017 – REVISED APRIL 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 6
6 Specifications......................................................... 8
6.1 Absolute Maximum Ratings ...................................... 8
6.2 ESD Ratings.............................................................. 8
6.3 Recommended Operating Conditions....................... 8
6.4 Thermal Information .................................................. 8
6.5 Electrical Characteristics........................................... 9
6.6 Timing Requirements .............................................. 12
6.7 Typical Characteristics ............................................ 15
7 Detailed Description ............................................ 20
7.1 Overview ................................................................. 20
7.2 Functional Block Diagram ....................................... 21
7.3 Feature Description................................................. 21
7.4 Device Functional Modes........................................ 41
7.5 Programming........................................................... 42
7.6 Register Maps ......................................................... 43
8 Application and Implementation ........................ 61
8.1 Application Information............................................ 61
8.2 Typical Application .................................................. 64
9 Power Supply Recommendations...................... 67
10 Layout................................................................... 68
10.1 Layout Guidelines ................................................. 68
10.2 Layout Example .................................................... 69
11 Device and Documentation Support ................. 70
11.1 Device Support...................................................... 70
11.2 Documentation Support ........................................ 70
11.3 Receiving Notification of Documentation Updates 70
11.4 Community Resources.......................................... 70
11.5 Trademarks ........................................................... 70
11.6 Electrostatic Discharge Caution ............................ 70
11.7 Glossary ................................................................ 70
12 Mechanical, Packaging, and Orderable
Information ........................................................... 71
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2018) to Revision C
Page
• Changed the maximum output frequency from 19 GHz to 20 GHz everywhere in the data sheet. The newly
recommended value for the DBLR_IBIAS_CTRL1 (R25[15:0]) extended the output frequency range and improved
high frequency performance. The old value (1572) for the DBLR_IBIAS_CTRL1 still supports up to 19-GHz output
and specs characterized in the Electrical Characteristics table. The new value (3115) provides a bonus in performance. . 1
• Deleted the recommended bypass capacitor values for Vcc pins 7, 11, 15, 21, 26 and 37, as these capacitor values
are not mandatory and the power supply filtering design is up to the user............................................................................ 7
• Added test condition "DBLR_IBIAS_CTRL1 = 1572" for POUT, LVCO2X and H1/2, in order to emphasize that these
data are taken while DBLR_IBIAS_CTRL1 is set to the old value (1572). With this register set to 3115, these specs
can be improved. The details can be found in the applications section................................................................................. 9
• Added a new row for VCO doubler output range in EC table with DBLR_IBIAS_CTRL1 set to 3115. The frequency
range is extended to 20 GHz.................................................................................................................................................. 9
• Added table note for EC table stating that the performance of 1/2 harmonic, output power and noise floor with
doubler enabled can be improved by setting DBLR_IBIAS_CTRL1 = 3115. ........................................................................ 9
• Changed all the 'FRAC_ORDER' to 'MASH_ORDER' to avoid confusion ........................................................................... 10
• Changed the names of timing specs to align with timing diagram: changed tCE to tES, tCS to tDCS, tCH to tCDH, and tCES
to tECS.................................................................................................................................................................................... 12
• Changed the names of timing specs to align with timing diagram: changed tES to tCE, tCES to tECS, added tDCS and
tCDH, and changed tCS to tCR.................................................................................................................................................. 13
• Changed the serial data input timing diagram and corrected the typo for 'SCK'.................................................................. 13
• Deleted the note 'The CSB transition from high to low must occur when SCK is low' from the serial data input timing
diagram, because SPI mode 4 (CPOL = 1, CPHA = 1) is also supported, and SCK is held high when idle in mode 4 ..... 13
• Added note for the serial data input timing diagram to explain the tCE requirement for mode 4 (CPOL = 1, CPHA = 1)
of SPI, because the diagram only indicated SPI mode 1 (CPOL = 0, CPHA = 0) ............................................................... 13
• Changed the serial data readback timing diagram............................................................................................................... 14
• Changed the note about MUXout clocking out and emphasized the effect of tCR on the readback data available time ..... 14
• Added phase noise plot for 16-, 17- and 20-GHz frequency output .................................................................................... 15
• Changed the phase noise plot for 18- and 19-GHz frequency output after changing DBLR_IBIAS_CTRL1
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Product Folder Links: LMX2595
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Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity LMX2595 SNAS736C – JUNE 2017 – REVISED APRIL 2019 LMX2595 20-GHz W ideband PLLATINUM™ RF Synthesizer Wit h Phase Synchronization and JESD204B Su pport 1 Features •1 10-MHz to 20-GHz output frequency • –110 dBc/Hz pha se noise at 100-kHz offset with 15-GHz carrier • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz) • Programmable o utput power • PLL key specifications – Figure of merit: –236 dBc/Hz – Normalized 1/f noise: –129 dBc/Hz – High phase detector frequency – 400- MHz integer mode – 300-MHz fractional mode – 32-bit fractional-N divider Remove integer boundary spurs with p rogrammable input multiplier • Synchr onization of output phase across multip le devices • Support for SYSREF with 9-ps resolution programmable delay • Frequency ramp and chirp generation abi lity for FMCW applications • < 20-µs VCO calibration speed • 3.3-V single power supply operation 2 Applications • 5G and mm-Wave wireless infras.
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