TMS320F28034 Microcontrollers Datasheet

TMS320F28034 Datasheet PDF, Equivalent


Part Number

TMS320F28034

Description

Microcontrollers

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download TMS320F28034 Datasheet


TMS320F28034
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TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584M – APRIL 2009 – REVISED JANUARY 2019
TMS320F2803x Piccolo™ Microcontrollers
1 Device Overview
1.1 Features
1
• High-Efficiency 32-Bit CPU (TMS320C28x)
– 60 MHz (16.67-ns Cycle Time)
– 16 × 16 and 32 × 32 MAC Operations
– 16 × 16 Dual MAC
– Harvard Bus Architecture
– Atomic Operations
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– Code-Efficient (in C/C++ and Assembly)
• Programmable Control Law Accelerator (CLA)
– 32-Bit Floating-Point Math Accelerator
– Executes Code Independently of the Main CPU
• Endianness: Little Endian
• JTAG Boundary Scan Support
– IEEE Standard 1149.1-1990 Standard Test
Access Port and Boundary Scan Architecture
• Low Cost for Both Device and System:
– Single 3.3-V Supply
– No Power Sequencing Requirement
– Integrated Power-on Reset and Brown-out
Reset
– Low Power
– No Analog Support Pins
• Clocking:
– Two Internal Zero-Pin Oscillators
– On-Chip Crystal Oscillator and External Clock
Input
– Watchdog Timer Module
– Missing Clock Detection Circuitry
• Up to 45 Individually Programmable, Multiplexed
GPIO Pins With Input Filtering
• Peripheral Interrupt Expansion (PIE) Block That
Supports All Peripheral Interrupts
• Three 32-Bit CPU Timers
• Independent 16-Bit Timer in Each Enhanced Pulse
Width Modulator (ePWM)
• On-Chip Memory
– Flash, SARAM, OTP, Boot ROM Available
• Code-Security Module
• 128-Bit Security Key and Lock
– Protects Secure Memory Blocks
– Prevents Firmware Reverse Engineering
• Serial Port Peripherals
– One Serial Communications Interface (SCI)
Universal Asynchronous Receiver/Transmitter
(UART) Module
– Two Serial Peripheral Interface (SPI) Modules
– One Inter-Integrated-Circuit (I2C) Module
– One Local Interconnect Network (LIN) Module
– One Enhanced Controller Area Network (eCAN)
Module
• Enhanced Control Peripherals
– ePWM
– High-Resolution PWM (HRPWM)
– Enhanced Capture (eCAP) Module
– High-Resolution Input Capture (HRCAP) Module
– Enhanced Quadrature Encoder Pulse (eQEP)
Module
– Analog-to-Digital Converter (ADC)
– On-Chip Temperature Sensor
– Comparator
• Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug Through Hardware
• Package Options
– 56-Pin RSH Very Thin Quad Flatpack (No Lead)
(VQFN)
– 64-Pin PAG Thin Quad Flatpack (TQFP)
– 80-Pin PN Low-Profile Quad Flatpack (LQFP)
• Temperature Options
– T: –40°C to 105°C
– S: –40°C to 125°C
– Q: –40°C to 125°C
(AEC Q100 Qualification for Automotive
Applications)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS320F28034
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584M – APRIL 2009 – REVISED JANUARY 2019
www.ti.com
1.2 Applications
Appliances
Building Automation
Electric Vehicle/Hybrid Electric Vehicle (EV/HEV)
Powertrain
Factory Automation
Grid Infrastructure
Medical, Healthcare and Fitness
Motor Drives
Power Delivery
Telecom Infrastructure
Test and Measurement
1.3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-
loop performance in real-time control applications such as industrial motor drives; solar inverters and
digital power; electrical vehicles and transportation; motor control; and sensing and signal processing. The
C2000 line includes the Delfino™ Premium Performance family and the Piccolo™ Entry Performance
family.
The F2803x Piccolo™ family of microcontrollers provides the power of the C28x core and Control Law
Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family
is code-compatible with previous C28x-based code, and also provides a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Enhancements have been made to the
HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit
references have been added and can be routed directly to control the PWM outputs. The ADC converts
from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC
interface has been optimized for low overhead and latency.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
PART NUMBER
Device Information(1)
PACKAGE
BODY SIZE
TMS320F28035PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28034PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28033PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28032PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28031PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28030PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28035PAG
TQFP (64)
10.0 mm × 10.0 mm
TMS320F28034PAG
TQFP (64)
10.0 mm × 10.0 mm
TMS320F28033PAG
TQFP (64)
10.0 mm × 10.0 mm
TMS320F28032PAG
TQFP (64)
10.0 mm × 10.0 mm
TMS320F28031PAG
TQFP (64)
10.0 mm × 10.0 mm
TMS320F28030PAG
TQFP (64)
10.0 mm × 10.0 mm
TMS320F28035RSH
VQFN (56)
7.0 mm × 7.0 mm
TMS320F28034RSH
VQFN (56)
7.0 mm × 7.0 mm
TMS320F28033RSH
VQFN (56)
7.0 mm × 7.0 mm
TMS320F28032RSH
VQFN (56)
7.0 mm × 7.0 mm
TMS320F28031RSH
VQFN (56)
7.0 mm × 7.0 mm
TMS320F28030RSH
VQFN (56)
7.0 mm × 7.0 mm
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
2 Device Overview
Copyright © 2009–2019, Texas Instruments Incorporated
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Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity TMS320F28030, TMS320F28031, TMS 320F28032 TMS320F28033, TMS320F28034, T MS320F28035 SPRS584M – APRIL 2009 REVISED JANUARY 2019 TMS320F2803x Pic colo™ Microcontrollers 1 Device Over view 1.1 Features 1 • High-Efficienc y 32-Bit CPU (TMS320C28x) – 60 MHz (1 6.67-ns Cycle Time) – 16 × 16 and 32 × 32 MAC Operations – 16 × 16 Dual MAC – Harvard Bus Architecture – A tomic Operations – Fast Interrupt Res ponse and Processing – Unified Memory Programming Model – Code-Efficient ( in C/C++ and Assembly) • Programmable Control Law Accelerator (CLA) – 32-B it Floating-Point Math Accelerator – Executes Code Independently of the Main CPU • Endianness: Little Endian • JTAG Boundary Scan Support – IEEE Sta ndard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture • Low Cost for Both Device and System: Single 3.3-V Supply – No Power Sequencing Requirement – Integrated Power-on Reset and Brown-out Reset –.
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