TMS320F2810

www.ti.com TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1 TMS320F2810, TMS320F2810-Q1, TTMMSS332200FF22881121,, TTMMSS332200FF22881112--QQ11 SPRS174V –TAMPSR3IL2200F0128–1R2E,VTISMEDS3FE2B0RFU2A8R1Y22-Q0211 SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021 TMS320F281x Digital Signal Processors 1 Features High-performance static CMOS technology – 150 MHz (6.67-ns cycle time) – Low-power (1.8-V core at 135 MHz, 1.9-V core at 150 MHz, 3.3-V I/O) design JTAG boundary scan support – IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture High-performance 32-bit CPU (TMS320C28x) – 16 × 16 and 32 × 32 MAC operations – 16 × 16 dual MAC – Harvard bus architecture – Atomic operations – Fast interrupt response and processing – Unified memory programming model – 4M linear program/data address reach – Code-efficient (in C/C++ and Assembly) – TMS320F24x/LF240x processor source code compatible On-chip memory – Up to 128K × 16 flash (Four 8K × 16 and six 16K × 16 sectors) – 1K × 16 OTP ROM – L0 and L1: 2 blocks of 4K × 16 each SingleAccess RAM (SARAM) – H0: 1 block of 8K × 16 SARAM – M0 and M1: 2 blocks of 1K × 16 each SARAM Boot ROM (4K × 16) – With software boot modes – Standard math tables External interface (F2812) – Over 1M × 16 total memory – Programmable wait states – Programmable read/write strobe timing – Three individual chip selects Endianness: Little endian Clock and system control – On-chip oscillator – Watchdog timer modul...