LMH1218 Driver Datasheet

LMH1218 Datasheet PDF, Equivalent


Part Number

LMH1218

Description

Low Power Ultra HD Cable Driver

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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LMH1218
SNLS474E – FEBRUARY 2015 – REVISED JUNE 2018
LMH1218 Low Power Ultra HD Cable Driver With Integrated Reclocker
1 Features
1 Supports ST-2082 (Proposed), ST-2081
(Proposed), SMPTE 424M, 344M, 292M, 259M,
DVB-ASI, SFF-8431 (SFP+) and 10GbE Ethernet
for SMPTE 2022-5/6
• Locks to Rates 11.88 Gbps, 5.94 Gbps, 2.97
Gbps, 1.485 Gbps, or Divided by 1.001 Sub-
Rates, DVB-ASI (270 Mbps) and 10GbE (10.3125
Gbps)
• Reference-Free Operation With Fast Lock Time
Covering All Supported or Selected Data Rates
• 75-Ω and 100-Ω Transmitter Outputs
• Integrated 2:1 Mux Input, 1:2 Demux/Fanout
Outputs
• Automatic Slew Rate Based on Input Rate Detect
• On-Chip Eye Monitor
• Low 300-mW Power Consumption With Automatic
Power Down on Loss of Input Signal
• Programmable Through SPI or SMBus Interface
• Single 2.5-V Supply Operation
• Small 4-mm × 4-mm 24-Pin WQFN Package
• –40°C to +85°C Operating Temperature Range
2 Applications
• UHDTV/4K/8K/HDTV/SDTV Video
• Digital Video Routers and Switches
• Digital Video Processing and Editing
• DVB-ASI and Distribution Amplifiers
• 10GbE for SMPTE 2022-5/6
3 Description
The LMH1218 device is a low-power cable driver with
integrated reclocker to drive serial video data
compatible to SMPTE-SDI, SMPTE 2022-5/6, 10GbE
Ethernet, and DVB-ASI standards. The LMH1218
supports up to 11.88 Gbps to enable Ultra High
Definition Video for 4K/8K applications. With 75-Ω
and 50-Ω transmitter outputs, the LMH1218 enables
multiple media options such as coax, fiber, and FR-4
PCB.
The integrated 2-to-1 MUX on the input of the
LMH1218 enables selection between two video
sources, while the programmable equalizer
compensates for the printed-circuit board loss to
extend signal reach. With a wide range clock-and-
data recovery (CDR) circuit, the on-chip reclocker
automatically detects and locks to serial data from
270 Mbps to 11.88 Gbps without the need for an
external reference clock and loop filter component,
thereby simplifying board design and lowering system
cost. The reclocked serial data can be routed to
either the 75-Ω or 50-Ω transmitter output, or both
simultaneously (1-to-2 fanout mode). The output
voltage swing is compatible to SFF-8431 (SFP+), ST-
2082/1 (Proposed), SMPTE 424M, 344M, 292M, and
259M standards.
A non-disruptive eye monitor allows for real-time
measurement of serial data to simplify system start-
up or field tuning. The LMH1218 can be programmed
using SPI or SMBus Interface.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMH1218
WQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified SPI Schematic
OUT
FPGA
OUT
MODE_SEL
ENABLE
4.7 PF
IN0+
100: Differential T-Line
IN0-
OUT
FPGA
OUT
4.7 PF
IN1+
100: Differential T-Line
IN1-
SS_N
SCK
MOSI
LOS_INT_N
MISO
LOCK
0.1 PF
VDD
0.01 PF
LMH1218
OUT0+
OUT0-
DAP
VSS
VSS
4.7 PF
: T-Line
4.7 PF
:
OUT1+
100: Differential T-Line
OUT1-
IN+
Optical Module
IN-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMH1218
LMH1218
SNLS474E – FEBRUARY 2015 – REVISED JUNE 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information .................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Recommended SMBus Interface AC Timing
Specifications ........................................................... 12
6.7 Serial Parallel Interface (SPI) Bus Interface AC
Timing Specifications ............................................... 12
6.8 Typical Characteristics ............................................ 13
7 Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 25
7.5 Programming .......................................................... 25
7.6 Register Maps ......................................................... 26
8 Application and Implementation ........................ 44
8.1 Application Information............................................ 44
8.2 Typical Application ................................................. 44
8.3 Do's and Don'ts ....................................................... 47
8.4 Initialization Set Up ................................................. 47
9 Power Supply Recommendations...................... 47
10 Layout................................................................... 48
10.1 Layout Guidelines ................................................. 48
10.2 Layout Example .................................................... 48
10.3 Solder Profile......................................................... 49
11 Device and Documentation Support ................. 50
11.1 Device Support...................................................... 50
11.2 Documentation Support ........................................ 50
11.3 Receiving Notification of Documentation Updates 50
11.4 Community Resources.......................................... 50
11.5 Trademarks ........................................................... 50
11.6 Electrostatic Discharge Caution ............................ 50
11.7 Glossary ................................................................ 50
12 Mechanical, Packaging, and Orderable
Information ........................................................... 50
4 Revision History
Changes from Revision D (December 2017) to Revision E
Page
• Changed the note under Float(Default) setting from: Reserved to: Power down until valid signal detected ......................... 5
• Changed MISO pin I/O description from 3-Level back to 2-Level .......................................................................................... 5
• Changed the Acknowledge (ACK) graphic text from: Clock Line Held Low by Receiver While Interrupt is Serviced to:
Host may held clock line low to delay transaction................................................................................................................ 20
• Changed Channel Register 0x80 default from: 0xXX to: 0x20 ............................................................................................ 43
• Changed the OUT0_VOD bit 7 default from x to 0............................................................................................................... 43
• Changed the bit description for the OUT0_VOD bits 7-3 from: drv_0_sel_vod[3:0] default value may change from
part to part to: drv_0_sel_vod[3:0] is typically 42 mV per step. ........................................................................................... 43
• Changed the OUT0_VOD bit 6 default from x to 0............................................................................................................... 43
• Changed the OUT0_VOD bit 5 default from x to 1............................................................................................................... 43
• Changed the OUT0_VOD bit 4 default from x to 0............................................................................................................... 43
Changes from Revision C (December 2016) to Revision D
Page
• Changed Channel Register 0x80 default value from 0101 0100’b to XXXX 0000’b ............................................................ 43
Changes from Revision B (February 2016) to Revision C
Page
• Changed MISO pin I/O description from 2-Level to 3-Level................................................................................................... 5
• Added test conditions to the source transmit differential launch amplitude parameters ........................................................ 7
• Changed OUT0 VOD_Scaling_PD description for bits 7 through 4 ..................................................................................... 43
2 Submit Documentation Feedback
Product Folder Links: LMH1218
Copyright © 2015–2018, Texas Instruments Incorporated


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity LMH1218 SNLS474E – FEBRUARY 2 015 – REVISED JUNE 2018 LMH1218 Low P ower Ultra HD Cable Driver With Integra ted Reclocker 1 Features •1 Supports ST-2082 (Proposed), ST-2081 (Proposed) , SMPTE 424M, 344M, 292M, 259M, DVB-ASI , SFF-8431 (SFP+) and 10GbE Ethernet fo r SMPTE 2022-5/6 • Locks to Rates 11. 88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gb ps, or Divided by 1.001 SubRates, DVB-A SI (270 Mbps) and 10GbE (10.3125 Gbps) • Reference-Free Operation With Fast Lock Time Covering All Supported or Sel ected Data Rates • 75-Ω and 100-Ω T ransmitter Outputs • Integrated 2:1 M ux Input, 1:2 Demux/Fanout Outputs • Automatic Slew Rate Based on Input Rate Detect • On-Chip Eye Monitor • Low 300-mW Power Consumption With Automati c Power Down on Loss of Input Signal Programmable Through SPI or SMBus Int erface • Single 2.5-V Supply Operatio n • Small 4-mm × 4-mm 24-Pin WQFN Package • –40°C to +85°C Operating Temperature Range 2 .
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