THC63LVDF84C Receiver Datasheet

THC63LVDF84C Datasheet PDF, Equivalent


Part Number

THC63LVDF84C

Description

24bit Color LVDS Receiver

Manufacture

CEL

Total Page 15 Pages
Datasheet
Download THC63LVDF84C Datasheet


THC63LVDF84C
THC63LVDF84C_Rev.1.20_E
THC63LVDF84C
24bit Color LVDS Receiver (Falling Edge Strobe Output)
General Description
The THC63LVDF84C receiver supports wide
temperature range as -40 to +85C, and wide
frequency range as 8 to 112MHz.
The THC63LVDF84C converts the four LVDS data
streams back into 24bits of LVCMOS data with
falling edge clock. At a transmit clock frequency of
112MHz, 24bits of RGB data and 4bits of timing and
control data (HSYNC, VSYNC, DE, etc.) are
transmitted at an effective rate of 3.1Gbps.
Application
Medium and Small Size Panel
Security Camera
Multi Function Printer
Machine Vision (Frame Grabber Board)
Medical Equipment Monitor
Features
1:7 LVDS to LVCMOS Deserializer
Operating Temperature Range : -40 to +85C
No Special Start-up Sequence Required
Spread Spectrum Clocking Tolerant up to 100kHz
Frequency Modulation and +/-2.5% Deviations
Pixel Clock Range: 8 to 112MHz
56pin TSSOP Package
Power Down Mode
Falling Edge Strobe Output
EU RoHS Compliant
Recommended LVDS Transmitter ICs
THC63LVDM83D
THC63LVDM87
Block Diagram
RA +/-
RB +/-
LVDS Inputs
(56 to 784Mbps/ch) RC +/-
RD +/-
THC63LVDF84C
7
RA0-6
7
RB0-6
7 LVCMOS Outputs
RC0-6
7
RD0-6
RCLK +/-
(8 to 112MHz)
PLL CLKOUT
(8 to 112MHz)
/PDWN
Figure 1. Block Diagram
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THC63LVDF84C
THC63LVDF84C_Rev.1.20_E
Pin Diagram
RC3
RD6
RC4
GND
RC5
RC6
RD0
LVDS GND
RA-
RA+
RB-
RB+
LVDS VCC
LVDS GND
RC-
RC+
RCLK-
RCLK+
RD-
RD+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLKOUT
RA0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VCC
55 RC2
54 RC1
53 RC0
52 GND
51 RB6
50 RD5
49 RD4
48 VCC
47 RB5
46 RB4
45 RB3
44 GND
43 RB2
42 RD3
41 RD2
40 VCC
39 RB1
38 RB0
37 RA6
36 GND
35 RA5
34 RD1
33 RA4
32 RA3
31 VCC
30 RA2
29 RA1
Pin Description
Pin Name
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
RCLK+,
RCLK-
Pin #
10, 9
12, 11
16, 15
20, 19
18, 17
Figure 2. Pin Diagram
Direction
Input
Type
LVDS
Description
LVDS Data Inputs
LVDS Clock Inputs
RA0 ~ RA6
RB0 ~ RB6
RC0 ~ RC6
RD0 ~ RD6
CLKOUT
/PDWN
VCC
GND
LVDS VCC
LVDS GND
PLL VCC
PLL GND
27, 29, 30, 32, 33, 35, 37
38, 39, 43, 45, 46, 47, 51
53, 54, 55, 1, 3, 5, 6
7, 34, 41, 42, 49, 50, 2
26
25
31, 40, 48, 56
4, 28, 36, 44, 52
13
8, 14, 21
23
22, 24
Output
Input
LVCMOS
- Power
Table 1. Pin Description
Pixel Data Outputs
Pixel Clock Output
H : Normal Operation
L : Power Down (All outputs are pulled to
ground)
Power Supply Pins for LVCMOS outputs
and digital circuitry
Ground Pins for LVCMOS outputs and
digital circuitry
Power Supply Pins for LVDS inputs
Ground Pins for LVDS inputs
Power Supply Pins for PLL circuitry
Ground Pins for PLL circuitry
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THine Electronics, Inc.
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Features THC63LVDF84C_Rev.1.20_E THC63LVDF84C 24b it Color LVDS Receiver (Falling Edge St robe Output) General Description The T HC63LVDF84C receiver supports wide temp erature range as -40 to +85C, and wi de frequency range as 8 to 112MHz. The THC63LVDF84C converts the four LVDS dat a streams back into 24bits of LVCMOS da ta with falling edge clock. At a transm it clock frequency of 112MHz, 24bits of RGB data and 4bits of timing and contr ol data (HSYNC, VSYNC, DE, etc.) are tr ansmitted at an effective rate of 3.1Gb ps. Application ・Medium and Small Siz e Panel ・Security Camera ・Multi Fun ction Printer ・Machine Vision (Frame Grabber Board) ・Medical Equipment Mon itor Features ・1:7 LVDS to LVCMOS De serializer ・Operating Temperature Ran ge : -40 to +85C ・No Special Start -up Sequence Required ・Spread Spectru m Clocking Tolerant up to 100kHz Freque ncy Modulation and +/-2.5% Deviations Pixel Clock Range: 8 to 112MHz ・56p in TSSOP Package ・Power Down Mode ・Falling Edge Strobe Output ・EU RoHS Compliant Recommen.
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