NTE7476

NTE7476 Integrated Circuit TTL − Dual J−K Flip−Flop with Preset and Clear Description: The NTE7476 is a dual J−K flip−flop in a 16−Lead plastic DIP type package that contains two independent J−K positive−edge−triggered flip−flops with individual J−K clock, preset, and clear inputs. J−K input is loaded into the master while the clock is high and transferred to the slave on the high−to−low transition. J and K inputs must be stable while the clock is high. Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C Note 1. Voltage values are with respect to network ground terminal. Recommended Operating Conditions: Parameter Supply Voltage High−Level Input Voltage Low−Level Input Voltage High−Level Output Current Low−Level Output Current Pulse Duration CLK High CLK Low PRE or CLR Low Setup Time Before CLK  Input Hold Time Data After CLK  Operating Temperature Range Symbol VCC VIH VIL IOH IOL tw tsu th TA Min Typ Max Unit 4.75 5.0 5.25 V...