MC68120 CONTROLLER Datasheet

MC68120 Datasheet PDF, Equivalent


Part Number

MC68120

Description

INTELLIGENT PERIPHERAL CONTROLLER

Manufacture

Motorola

Total Page 30 Pages
PDF Download
Download MC68120 Datasheet PDF


MC68120
® ItIIOTOROLA
Advance Information
INTELLIGENT PERIPHERAL CONTROLLER
The MC68120/MC68121 Intelligent Peripheral Controller (lPCI is a
general purpose, mask programmable peripheral controller. The IPC
provides the interface between an M68000 or M6800 Family
microprocessor and the final peripheral devices through a system bus
and control lines. System bus data is transferred to and from the IPC via
dual-port RAM while the software utilizes the semaphore registers to
control RAM tasking or any other shared resource. Multiple operating
I modes range from a single chip mode with 21 I/O lines and 2 control
lines to an expanded mode supporting an address space of 64K bytes.
The MC68120 has 2K bytes of on-chip ROM to make full use of all
operating modes. The MC68121 utilizes only the expanded address
modes, due to the absence of on-chip ROM.
A serial communications interface, 16-bit timer, dual-ported RAM
and semaphore registers are available for use by the IPC in all operating
modes.
• System Bus Compatible with the Asynchronous M68000 Family
• System Bus Compatible with the MC6809 and Other M6800 Family
Processors/ Peripherals
• Local Bus Allows Interface with all M6800 Peripherals
• MC6801 Source and Object Code Compatible
• Upward Compatible with MC6800 Source and Object Code
• 2048 Bytes of ROM (MC68120 Only)
• 128 Bytes of Dual-Ported RAM
• Multiple Operation Modes Ranging from Single Chip to Expanded,
with 64K Byte Address Space
• Six Shared Semaphore Registers
• 21 Parallel I/O Lines and 2 Handshake Lines (5 I/O Lines on
MC68121)
• Serial Communications Interface (SCI)
• 16-Bit Three-Function Timer
• 8-Bit CPU and Internal Bus
• Halt/Bus Available Capability Control
• 8 x 8 Multiply Instruction
• TTL Compatible Inputs and Outputs
• External and Internal Interrupts
Package Type
Ceramic
L Suffix
GENERIC INFORMATION
(TA=O°C to 70°C)
Frequency (MHz)
1.0
1.0
1.25
1.25
Generic Number
MC68120Ll (Unicorn ROM)
MC68121 L
MC68120Ll-l (Unicorn ROM)
MC68121L-l
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
3-702
MC68120
MC68121
HMOS
(HIGH-DENSITY N-CHANNEL
SILICON-GATE)
INTELLIGENT PERIPHERAL
CONTROLLER
L SUFFIX
CERAMIC PACKAGE
CASE 740
PIN ASSIGNMENT
VSS
IRQl
HALTI
BA/NMI
E
SR/W
DTACK
CS
SA7
SA6
SA5
SA4
VCC
SA3
SA2
SAl
SAO
SDO
SDl
SD2
SD3
SD4
SD5
SD6 23
SD7 24
P24
P23
P22
P21
P20
SC2
SCl
P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47

MC68120
MC68120, MC68121
MC68120/MC68121 INTELLIGENT PERIPHERAL CONTROLLER - BLOCK DIAGRAM
~ N~:::n:J;:!;
(L (L (L (L (L
~6f->do<:~<t:~<t:
f-Ul~~
~-~~§;
HALT/BA/NMI ..
1RQ1
RESET
CPU
VSS
VCC
cs
SR/W
DTACK
SDl
SSDD2O]
:=SD3
J"-- SD4
SD5
SD6
SD7
SAO
SAl
SA2
SA3
SA4
SA5
SA6
SA7
I
gl~l~Single ChiP{gg g g ggg
Expanded Non-MultiPlexedtS(3 8 ~ 8 8 0 81~IQ
{g g"<DI!)'<:tMN~O
Expanded Multiplexed ~ ~ ~ ~ ~ ~ I~ ';l
<t:<t:<t:<t:<t:<t:<t:<t:a:
~~~~~~~~R~
MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature Range
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
eeramic Package
Symbol
Vce
Vin
TA
Tstg
Value
-0.3 to + 7.0
-0.3 to + 7.0
o to 70
-55 to + 150
Unit
V
V
De
De
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however. it is ad-
vised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high-
impedance circuit. For proper operation it is
recommended that Vin and Vout be con-
strained to the range V SS s (Vin or
VoutsVee.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g .• either
VSS or Vee).
3-703


Features ® ItIIOTOROLA Advance Information INTEL LIGENT PERIPHERAL CONTROLLER The MC6812 0/MC68121 Intelligent Peripheral Contro ller (lPCI is a general purpose, mask p rogrammable peripheral controller. The IPC provides the interface between an M 68000 or M6800 Family microprocessor an d the final peripheral devices through a system bus and control lines. System bus data is transferred to and from the IPC via dual-port RAM while the softwa re utilizes the semaphore registers to control RAM tasking or any other shared resource. Multiple operating I modes r ange from a single chip mode with 21 I/ O lines and 2 control lines to an expan ded mode supporting an address space of 64K bytes. The MC68120 has 2K bytes of on-chip ROM to make full use of all op erating modes. The MC68121 utilizes onl y the expanded address modes, due to th e absence of on-chip ROM. A serial comm unications interface, 16-bit timer, dua l-ported RAM and semaphore registers ar e available for use by the IPC in all operating modes. • System .
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