SiRA54DP MOSFET Datasheet

SiRA54DP Datasheet PDF, Equivalent


Part Number

SiRA54DP

Description

N-Channel 40V (D-S) MOSFET

Manufacture

Vishay

Total Page 13 Pages
Datasheet
Download SiRA54DP Datasheet


SiRA54DP
www.vishay.com
SiRA54DP
Vishay Siliconix
N-Channel 40 V (D-S) MOSFET
PRODUCT SUMMARY
VDS (V)
40
RDS(on) () (MAX.)
0.00235 at VGS = 10 V
0.00320 at VGS = 4.5 V
ID (A) a, g
60
60
Qg (TYP.)
32 nC
PowerPAK® SO-8 Single
D
D8
D7
D6
5
6.15 mm
1
Top View
5.15 mm
1
2S
3S
4S
G
Bottom View
Ordering Information:
SiRA54DP-T1-GE3 (lead (Pb)-free and halogen-free)
FEATURES
• TrenchFET® Gen IV power MOSFET
• 100 % Rg and UIS tested
• Tuned for the lowest RDS-Qoss FOM
• Qgd / Qgs ratio < 1 optimizes switching
characteristics
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Synchronous rectification
• High power density DC/DC
• VRMs and embedded DC/DC
• DC/AC inverters
• Load switch
G
D
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Pulsed Drain Current (t = 100 μs)
Continuous Source-Drain Diode Current
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature) d, e
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
TC = 25 °C
TA = 25 °C
L = 0.1 mH
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
VDS
VGS
ID
IDM
IS
IAS
EAS
PD
TJ, Tstg
LIMIT
40
+20, -16
60 g
60 g
32.2 b, c
25.7 b, c
150
33.3
4 b, c
30
45
36.7
23.5
4.4 b, c
2.8 b, c
-55 to +150
260
UNIT
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient b, f
Maximum Junction-to-Case (Drain)
t 10 s
Steady State
SYMBOL
RthJA
RthJC
TYPICAL
24
2.5
MAXIMUM
28
3.4
UNIT
°C/W
Notes
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 70 °C/W.
g. Package limited.
S16-1049-Rev. A, 30-May-16
1
Document Number: 76466
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiRA54DP
www.vishay.com
SiRA54DP
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
On-State Drain Current a
Drain-Source On-State Resistance a
Forward Transconductance a
Dynamic b
VDS
VDS/TJ
VGS(th)/TJ
VGS(th)
IGSS
IDSS
ID(on)
RDS(on)
gfs
VGS = 0 V, ID = 250 μA
ID = 250 μA
VDS = VGS, ID = 250 μA
VDS = 0 V, VGS = +20, -16 V
VDS = 40 V, VGS = 0 V
VDS = 40 V, VGS = 0 V, TJ = 55 °C
VDS 5 V, VGS = 10 V
VGS = 10 V, ID = 15 A
VGS = 4.5 V, ID = 10 A
VDS = 10 V, ID = 15 A
40 - - V
- 24 -
mV/°C
- -5.2 -
1.1 - 2.3 V
-
-
± 100
nA
- -1
μA
- - 10
30 - - A
- 0.00195 0.00235
- 0.00265 0.00320
- 106 -
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Crss/Ciss Ratio
Total Gate Charge
Ciss
Coss
Crss
Qg
VDS = 20 V, VGS = 0 V, f = 1 MHz
VDS = 20 V, VGS = 10 V, ID = 10 A
- 5300 -
- 707 -
pF
- 105 -
- 0.020 0.040
- 69 104
- 32 48
Gate-Source Charge
Gate-Drain Charge
Output Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Qgs
Qgd
Qoss
Rg
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
VDS = 20 V, VGS = 4.5 V, ID = 10 A
VDS = 20 V, VGS = 0 V
f = 1 MHz
VDD = 20 V, RL = 2
ID 10 A, VGEN = 10 V, Rg = 1
VDD = 20 V, RL = 2
ID 10 A, VGEN = 4.5 V, Rg = 1
- 13.5 -
nC
- 6.9 -
- 30.5 -
0.4 1.1 2.0
- 8 16
- 8 16
- 28 56
- 7 14
ns
- 24 48
- 69 138
- 23 46
- 10 20
Continuous Source-Drain Diode Current
Pulse Diode Forward Current (tp = 100 μs)
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
IS
ISM
VSD
trr
Qrr
ta
tb
TC = 25 °C
IS = 5 A
IF = 10 A, dI/dt = 100 A/μs,
TJ = 25 °C
- - 33.3
A
- - 150
- 0.72 1.1 V
- 44 88 ns
- 58 116 nC
- 29 -
ns
- 15 -
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S16-1049-Rev. A, 30-May-16
2
Document Number: 76466
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000


Features www.vishay.com SiRA54DP Vishay Siliconi x N-Channel 40 V (D-S) MOSFET PRODUCT SUMMARY VDS (V) 40 RDS(on) () (MA X.) 0.00235 at VGS = 10 V 0.00320 at VG S = 4.5 V ID (A) a, g 60 60 Qg (TYP.) 32 nC PowerPAK® SO-8 Single D D8 D7 D6 5 6.15 mm 1 Top View 5.15 mm 1 2S 3S 4S G Bottom View Ordering Inform ation:  SiRA54DP-T1-GE3 (lead (Pb)- free and halogen-free) FEATURES • Tr enchFET® Gen IV power MOSFET • 100 % Rg and UIS tested • Tuned for the lo west RDS-Qoss FOM • Qgd / Qgs ratio < 1 optimizes switching characteristics • Material categorization: for defini tions of compliance please see www.vish ay.com/doc?99912 APPLICATIONS • Sync hronous rectification • High power de nsity DC/DC • VRMs and embedded DC/DC • DC/AC inverters • Load switch G D S N-Channel MOSFET ABSOLUTE MAXIM UM RATINGS (TA = 25 °C, unless otherwi se noted) PARAMETER SYMBOL Drain-Sou rce Voltage Gate-Source Voltage Continu ous Drain Current (TJ = 150 °C) Pulsed Drain Current (t = 100 μs) Continuous Source-Drain .
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