MCUs. RX23W Datasheet

RX23W MCUs. Datasheet pdf. Equivalent

RX23W Datasheet
Recommendation RX23W Datasheet
Part RX23W
Description MCUs
Feature RX23W; Datasheet RX23W Group Renesas MCUs R01DS0342EJ0100 Rev.1.00 Aug 06, 2019 54-MHz 32-bit RX MCUs, b.
Manufacture Renesas
Datasheet
Download RX23W Datasheet





Renesas RX23W
Datasheet
RX23W Group
Renesas MCUs
R01DS0342EJ0100
Rev.1.00
Aug 06, 2019
54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory,
Bluetooth5.0, various communication functions including USB 2.0 full-speed host/function/OTG, CAN,
SD host interface, serial sound interface, capacitive touch sensing unit, 12-bit A/D converter,
12-bit D/A converter, RTC, Encryption functions
Features
■ 32-bit RXv2 CPU core
Max. operating frequency: 54 MHz
Capable of 88.56 DMIPS in operation at 54 MHz
Enhanced DSP: 32-bit multiply-accumulate and 16-bit
multiply-subtract instructions supported
Built-in FPU: 32-bit single-precision floating point (compliant to
IEEE754)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Memory protection unit (MPU) supported
■ Low power design and architecture
Operation from a single 1.8-V to 3.6-V supply
RTC capable of operating on the battery backup power supply
Three low power consumption modes
Low power timer (LPT) that operates during the software standby state
■ On-chip flash memory for code
384- to 512-Kbyte capacities
On-board or off-board user programming
Programmable at 1.8 V
For instructions and operands
■ On-chip data flash memory
8 Kbytes (1,000,000 program/erase cycles (typ.))
BGO (Background Operation)
■ On-chip SRAM, no wait states
64-Kbyte size capacities
■ Data transfer functions
DMAC: Incorporates four channels
DTC: Four transfer modes
■ ELC
Module operation can be initiated by event signals without using
interrupts.
Linked operation between modules is possible while the CPU is sleeping.
■ Reset and supply management
Eight types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock functions
Main clock oscillator frequency: 1 to 20 MHz
External clock input frequency: Up to 20 MHz
Sub-clock oscillator frequency: 32.768 kHz
Frequency of Bluetooth-dedicated clock oscillator: 32 MHz
PLL circuit input: 4 MHz to 12.5 MHz
On-chip low- and high-speed oscillators, dedicated on-chip low-speed
oscillator for the IWDT
USB-dedicated PLL circuit: 4, 6, 8, or 12 MHz
54 MHz can be set for the system clock and 48 MHz for the USB clock
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
■ Realtime clock
Adjustment functions (30 seconds, leap year, and error)
Calendar count mode or binary count mode selectable
Time capture function
Time capture on event-signal input through external pins
■ Independent watchdog timer
15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
■ Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance functions for
the A/D converter, clock frequency accuracy measurement circuit,
independent watchdog timer, RAM test assistance functions using the
DOC, etc.
■ MPC
Input/output functions selectable from multiple pins
R01DS0342EJ0100 Rev.1.00
Aug 06, 2019
PTBG0085KB-A 5.5 × 5.5 mm, 0.5 mm pitch
PVQN0056LA-A 7 × 7 mm, 0.4 mm pitch
■ Up to 12 communication functions
Bluetooth Low Energy (1 channel)
An RF transceiver and link layer compliant with the Bluetooth 5.0 Low
Energy specification
LE 1M PHY, LE 2M PHY, LE Coded PHY (125 kbps and 500 kbps),
and LE Advertising extension support
On-chip Bluetooth-dedicated AES-CCM (128-bit blocks) encryption
circuit
USB 2.0 host/function/On-The-Go (OTG) (one channel),
full-speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and
BC (Battery Charger) supported
CAN (one channel) compliant to ISO11898-1:
Transfer at up to 1 Mbps
SCI with many useful functions (up to 4 channels)
Asynchronous mode, clock synchronous mode, smart card interface
Reduction of errors in communications using the bit modulation
function
IrDA interface (one channel, in cooperation with the SCI5)
I2C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
RSPI (one channel): Transfer at up to 16 Mbps
Serial sound interface (one channel)
SD host interface (optional: one channel) SD memory/ SDIO 1-bit or
4-bit SD bus supported
■ Up to 19 extended-function timers
16-bit MTU: input capture, output compare, complementary PWM
output, phase counting mode (five channels)
16-bit TPU: input capture, output compare, phase counting mode (six
channels)
8-bit TMR (four channels)
16-bit compare-match timers (four channels)
■ 12-bit A/D converter
Capable of conversion within 0.83 μs
14 channels
Sampling time can be set for each channel
Self-diagnostic function and analog input disconnection detection
assistance function
■ 12-bit D/A converter
Two channels
■ Capacitive touch sensing unit
Self-capacitance method: A single pin configures a single key,
supporting up to 12 keys
Mutual capacitance method: Matrix configuration with 12 pins, supporting
up to 36 keys
■ Analog comparator
Two channels × one unit
■ General I/O ports
5-V tolerant, open drain, input pull-up, switching of driving capacity
■ Encryption functions (TSIP-Lite)
Unauthorized access to the encryption engine is disabled and
imposture and falsification of information are prevented
Safe management of keys
128- or 256-bit key length of AES for ECB, CBC, GCM, others
True random number generator
■ Temperature sensor
■ Operating temperature range
 40 to +85C
■ Applications
General industrial and consumer equipment
Page 1 of 96



Renesas RX23W
RX23W Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1
Outline of Specifications (1/4)
Classification
CPU
Module/Function
CPU
Memory
FPU
ROM
RAM
E2 DataFlash
MCU operating mode
Clock
Clock generation circuit
Resets
Voltage detection Voltage detection circuit
(LVDAb)
Description
Maximum operating frequency: 54 MHz
32-bit RX CPU (RX v2)
Minimum instruction execution time: One instruction per clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
Basic instructions: 75 (variable-length instruction format)
Floating-point instructions: 11
DSP instructions: 23
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit
On-chip divider: 32-bit ÷ 32-bit → 32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
Single precision (32-bit) floating point
Data types and floating-point exceptions in conformance with the IEEE754 standard
Capacity: 384/512 Kbytes
Up to 32 MHz: No-wait memory access
32 to 54 MHz: Wait state required. No wait state if the instruction is served by a ROM accelerator hit.
Programming/erasing method:
Serial programming (asynchronous serial communication/USB communication), self-programming
Capacity: 64 Kbytes
54 MHz, no-wait memory access
Capacity: 8 Kbytes
Number of erase/write cycles: 1,000,000 (typ)
Single-chip mode
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, USB-dedicated PLL frequency synthesizer, and IWDT-dedicated on-chip
oscillator, Bluetooth-dedicated clock oscillator, Bluetooth-dedicated low-speed on-chip oscillator
Oscillation stop detection: Available
Clock frequency accuracy measurement circuit (CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 54 MHz (at max.)
MTU2a runs in synchronization with the PCLKA: 54 MHz (at max.)
The ADCLK for the S12AD runs in synchronization with the PCLKD: 54 MHz (at max.)
Peripheral modules other than MTU2a and S12ADE run in synchronization with the PCLKB: 32 MHz
(at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog
timer reset, and software reset
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 3 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels
R01DS0342EJ0100 Rev.1.00
Aug 06, 2019
Page 2 of 96



Renesas RX23W
RX23W Group
1. Overview
Table 1.1
Outline of Specifications (2/4)
Classification Module/Function
Description
Low power
consumption
Low power consumption
functions
Module stop function
Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Low power timer that operates during the software standby state
Function for lower operating Operating power control modes
power consumption
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt
Interrupt controller (ICUb)
Interrupt vectors: 148
External interrupts: 7 (NMI, IRQ0, IRQ1, IRQ4 to IRQ7 pins)
Non-maskable interrupts: 6 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, WDT interrupt, IWDT interrupt, and VBATT power monitoring interrupt)
16 levels specifiable for the order of priority
DMA
DMA controller (DMACA)
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
Data transfer controller
(DTCa)
Transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
I/O ports
General I/O ports
Event link controller (ELC)
85-pin/56-pin
I/O: 43/29
Input: 1/1
Pull-up resistors: 43/29
Open-drain outputs: 31/24
5-V tolerance: 5/4
Event signals of 59 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for port B and port E
Multi-function pin controller (MPC)
Capable of selecting the input/output function from multiple pins
Timers
16-bit timer pulse unit
(TPUa)
(16 bits × 6 channels) × 1 unit
Maximum of 10 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Supports the input capture/output compare function
Output of PWM waveforms in up to 9 phases in PWM mode
Support for buffered operation, phase-counting mode (two-phase encoder input) and cascade
connected operation (32 bits × 2 channels) depending on the channel.
Capable of generating conversion start triggers for the A/D converters
Signals from the input capture pins are input via a digital filter
Clock frequency measuring method
Multi-function timer pulse
unit 2 (MTU2a)
(16 bits × 5 channels) × 1 unit
Up to 15 pulse-input/output lines are available based on the six 16-bit timer channels
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD).
Input capture function
18 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Capable of generating conversion start triggers for the A/D converter
Port output enable 2
(POE2a)
Controls the high-impedance state of the MTU’s waveform output pins
Compare match timer
(CMT)
(16 bits × 2 channels) × 2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Watchdog timer (WDTA)
14 bits × 1 channel
Select from among six counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512, PCLK/
2048, PCLK/8192)
R01DS0342EJ0100 Rev.1.00
Aug 06, 2019
Page 3 of 96





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