Haptic Driver. DRV2604L Datasheet

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DRV2604L Datasheet
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Part DRV2604L
Description Haptic Driver
Feature DRV2604L; Product Folder Order Now Technical Documents Tools & Software Support & Community DRV2604L SLOS.
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Texas Instruments DRV2604L
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Technical
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DRV2604L
SLOS866F – MAY 2014 – REVISED MARCH 2018
DRV2604L 2- to 5.2-V Haptic Driver for LRA and ERM
with Internal Memory and Smart-Loop Architecture
1 Features
1 Flexible Haptic and Vibration Driver
– LRA (Linear Resonance Actuator)
– ERM (Eccentric Rotating Mass)
• I2C-Controlled Digital Playback Engine
– Waveform Sequencer and Trigger
– Real-Time Playback Mode through I2C
– Internal RAM for Customized Waveforms
– I2C Dual-Mode Drive (Open and Closed Loop)
• Smart-Loop Architecture (Patent Pending Control
Algorithm)
– Automatic Overdrive and Braking
– Automatic Resonance Tracking and Reporting
(LRA Only)
– Automatic Actuator Diagnostic
– Automatic Level Calibration
– Wide Support for Actuator Models
• Immersion TouchSense® 3000 Compatible
• Drive Compensation Over Battery Discharge
• Wide Voltage Operation (2 V to 5.2 V)
• Efficient Differential Switching Output Drive
• PWM Input with 0% to 100% Duty-Cycle Control
Range
• Hardware Trigger Input
• Fast Startup Time
• 1.8-V Compatible, VDD-Tolerant Digital Interface
2 Applications
• Mobile Phones
• Tablets
3 Description
The DRV2604L device is a low-voltage haptic driver
that provides a closed-loop actuator-control system
for high-quality tactile feedback for ERM and LRA.
This schema helps improve actuator performance in
terms of acceleration consistency, start time, and
brake time and is accessible through a shared I2C
compatible bus or PWM input signal.
The DRV2604L device includes enough integrated
RAM to allow the user to pre-load over 100
customized smart-loop architecture waveforms.
These waveforms can be instantly played back
through I2C or optionally triggered through a
hardware trigger terminal.
Additionally, the real-time playback mode allows the
host processor to bypass the memory playback
engine and play waveforms directly from the host
through I2C.
The smart-loop architecture inside the DRV2604L
device allows simple auto-resonant drive for the LRA
as well as feedback-optimized ERM drive allowing for
automatic overdrive and braking. The smart-loop
architecture creates a simplified input waveform
interface as well as reliable motor control and
consistent motor performance. The DRV2604L device
also features automatic transition to an open-loop
system in the event that an LRA actuator is not
generating a valid back-EMF voltage. When the LRA
generates a valid back-EMF voltage, the DRV2604L
device automatically synchronizes with the LRA. The
DRV2604L also allows for open-loop driving through
the use of internally-generated PWM.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (MAX)
DRV2604L
DSBGA (9)
1.50 mm × 1.50 mm
DRV2604L
VSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VDD
Supply
correction
RAM
Gate
drive
OUT+
SDA
SCL
EN
IN/TRIG
REG
2
I C I/F
REG
Control and
playback engine
Back-EMF
detection
Gate
drive
LRA
M or
ERM
OUTt
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments DRV2604L
DRV2604L
SLOS866F – MAY 2014 – REVISED MARCH 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements ................................................ 6
6.7 Switching Characteristics .......................................... 6
6.8 Typical Characteristics .............................................. 8
7 Parameter Measurement Information .................. 9
7.1 Test Setup for Graphs............................................... 9
8 Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 19
8.5 Programming........................................................... 22
8.6 Register Map........................................................... 35
9 Application and Implementation ........................ 54
9.1 Application Information............................................ 54
9.2 Typical Application .................................................. 55
9.3 Initialization Setup ................................................... 58
10 Power Supply Recommendations ..................... 59
11 Layout................................................................... 60
11.1 Layout Guidelines ................................................. 60
11.2 Layout Example .................................................... 61
12 Device and Documentation Support ................. 62
12.1 Documentation Support ........................................ 62
12.2 Receiving Notification of Documentation Updates 62
12.3 Community Resource............................................ 62
12.4 Trademarks ........................................................... 62
12.5 Electrostatic Discharge Caution ............................ 62
12.6 Glossary ................................................................ 62
13 Mechanical, Packaging, and Orderable
Information ........................................................... 62
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2016) to Revision F
Page
• Changed the DEFAULT value for bit 5-4 of Table 19 From: 1 To 3 ................................................................................... 46
• Changed the DEFAULT value for bit 3-2 of Table 19 From: 2 To 1 ................................................................................... 47
• Changed the DEFAULT value for bit 1-0 of Table 19 From: 2 To 1 ................................................................................... 48
• Changed the typical value of C(VDD) in Table 29 From: 0.1 µF To: 1 µF .............................................................................. 54
Changes from Revision D (June 2015) to Revision E
Page
Table 2, changed 0x00 Bit 4 From: Reserved To: ILLEGAL_ADDR.................................................................................... 35
Status (Address: 0x00), changed 0x00 Bit 4 From: Reserved To: ILLEGAL_ADDR ........................................................... 36
Changes from Revision C (September 2014) to Revision D
Page
• Released full version of the data sheet ................................................................................................................................. 1
2 Submit Documentation Feedback
Product Folder Links: DRV2604L
Copyright © 2014–2018, Texas Instruments Incorporated



Texas Instruments DRV2604L
www.ti.com
5 Pin Configuration and Functions
YZF Package
9-Pin DSBGA With 0.5-mm Pitch
(Top View)
123
DRV2604L
SLOS866F – MAY 2014 – REVISED MARCH 2018
A
EN
REG
OUT+
B
IN/TRIG
SDA
GND
C
SCL
VDD
OUT±
Not to scale
PIN
NO. NAME
A1 EN
A2 REG
A3 OUT+
B1 IN/TRIG
B2 SDA
B3 GND
C1 SCL
C3 OUT–
C2 VDD
TYPE (1)
I
O
O
I
I/O
P
I
O
P
Pin Functions
DESCRIPTION
Device enable
The REG pin is the 1.8-V regulator output. A 1-µF capacitor is required.
Positive haptic driver differential output
Multi-mode Input. I2C selectable as PWM, analog, or trigger. If not used, this pin should
be connected to GND
I2C data
Supply ground
I2C clock
Negative haptic-driver differential output
Supply input (2 to 5.2 V). A 1-µF capacitor is required.
(1) I = input, O = output, I/O = input and output, P = power
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: DRV2604L
Submit Documentation Feedback
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