Buck Controller. TPS40422 Datasheet

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TPS40422 Datasheet
Recommendation TPS40422 Datasheet
Part TPS40422
Description Dual-Output or Two-Phase Synchronous Buck Controller
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Texas Instruments TPS40422
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
TPS40422
SLUSAQ4F – OCTOBER 2011 – REVISED JANUARY 2017
TPS40422 Dual-Output or Two-Phase Synchronous Buck Controller
with PMBus™ Interface
1 Features
1 Single Supply Operation: 4.5 V to 20 V
• Output Voltage from 0.6 V to 5.6 V
• Dual-output or Two-Phase Synchronous Buck
Controller
• PMBus™ Interface Capability
– Margining Up or Down with 2-mV Step
– Programmable Fault Limit and Response
– Output Voltage, Output Current Monitoring
– External Temperature Monitoring with 2N3904
Transistor
– Programmable UVLO ON and OFF Thresholds
– Programmable Soft-start Time and Turn-On
and Turn-Off Delay
• On-Chip Non-volatile Memory (NVM) to Store
Custom Configurations
• 180° Out-of-Phase to Reduce Input Ripple
• 600-mV Reference Voltage with ±0.5% Accuracy
from 0°C to 85°C
• Inductor DCR Current Sensing
• Programmable Switching Frequency: 200 kHz to
1 MHz
• Voltage Mode Control with Input Feed Forward
• Current Sharing for Multiphase Operation
• Supports Pre-biased Output
• Differential Remote Sensing
• External SYNC
• BPEXT Pin Boosts Efficiency by Supporting
External Bias Power Switch Over
• OC, OV, UV, and OT Fault Protection
• 40-Pin, 6 mm × 6 mm VQFN Package with 0.5-
mm Pitch
• 40-Pin, 5 mm × 5 mm WQFN Package with 0.4-
mm Pitch
2 Applications
• Multiple Rail Systems
• Telecom Base Station
• Switcher/Router Networking
• Server and Storage System
3 Description
The TPS40422 is a dual-output PMBus protocol,
synchronous buck controller. It can be configured
also for a single, two-phase output.
The wide input range supports 5-V and 12-V
intermediate buses. The accurate reference voltage
satisfies the need of precision voltage to the modern
ASICs and potentially reduces the output
capacitance. Voltage mode control reduces noise
sensitivity and also ensures low duty ratio conversion.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS40422
VQFN (40)
WQFN (40)
6.00 mm × 6.00 mm
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Application
VOUT1
CLK
DATA
SMBALRT
SYNC
12 CLK
31
VDD
BP3 32
11 DATA
ADDR1 9
13 SMBALRT
ADDR0 10
40 SYNC
RT 1
PG1 33 PG1
CNTL1 4 CNTL1
PG2 19
CNTL2 5
TPS40422
29 HDRV1
HDRV2 21
30 BOOT1
BOOT2 20
28 SW1
SW2 22
PG2
CNTL2
VIN
VOUT2
27 LDRV1
26 PGND
34 CS1P
35 CS1N
37 VSNS1
39 DIFFO1
LDRV2 23
CS2P 18
CS2N 17
VSNS2 15
2 FB1
FB2 8
3 COMP1
38 GSNS1
COMP2 7
GSNS2 14
36 6 24 25 16
UDG-11278
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments TPS40422
TPS40422
SLUSAQ4F – OCTOBER 2011 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 4
7 Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Electrical Characteristics........................................... 7
7.5 Typical Characteristics ............................................ 11
8 Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 23
8.5 Programming .......................................................... 26
8.6 Register Maps ........................................................ 27
9 Applications and Implementation ...................... 51
9.1 Application Information............................................ 51
9.2 Typical Application ................................................. 51
10 Power Supply Recommendations ..................... 60
11 Layout................................................................... 61
11.1 Layout Guidelines ................................................. 61
11.2 Layout Example .................................................... 62
12 Device and Documentation Support ................. 63
12.1 Device Support...................................................... 63
12.2 Community Resources.......................................... 63
12.3 Trademarks ........................................................... 63
12.4 Electrostatic Discharge Caution ............................ 63
12.5 Glossary ................................................................ 63
13 Mechanical, Packaging, and Orderable
Information ........................................................... 63
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2016) to Revision F
Page
• Added WQFN package to Device Information table............................................................................................................... 1
• Added WQFN package drawing ............................................................................................................................................. 4
Changes from Revision D (August 2014) to Revision E
Page
• Added pins (CS1N, CS2N, CS1P, CS2P, GSNS1, and GSNS2) to Input voltage range specification in Absolute
Maximum Ratings table .......................................................................................................................................................... 6
• Updated VSNSx connection description in Table 1 ............................................................................................................ 22
• Updated VSNS2 connection description in Table 2 ............................................................................................................ 25
• Corrected Equation 23.......................................................................................................................................................... 54
• Clarified Table 9 ................................................................................................................................................................... 55
2 Submit Documentation Feedback
Product Folder Links: TPS40422
Copyright © 2011–2017, Texas Instruments Incorporated



Texas Instruments TPS40422
www.ti.com
TPS40422
SLUSAQ4F – OCTOBER 2011 – REVISED JANUARY 2017
Changes from Revision C (August 2012) to Revision D
Page
• Added Handling Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
• Corrected Simplified Application ............................................................................................................................................ 1
• Updated FB2 description in table ........................................................................................................................................... 5
• Changed maximum input voltage range for VDD from "20 V" to "22 V" in Absolute Maximum Ratings table ...................... 6
• Corrected maximum input voltage range for CLK, DATA, and SYNC to "5.5 V" in Absolute Maximum Ratings table ......... 6
• Corrected maximum input voltage range for CNTL1, CNTL2 to "7 V" in Absolute Maximum Ratings table ........................ 6
• Corrected maximum output voltage range for SMBALRT in Absolute Maximum Ratings table ........................................... 6
• Updated specifications in PMBus INTERFACE section of Electrical Characteristics table.................................................. 10
• Added Switching Node and BOOT Voltage section ............................................................................................................. 19
• Changed section title from User Data and Adjustable Anti-Cross Conduction Delay to User Data..................................... 22
• Updated User Data section .................................................................................................................................................. 22
• Added Adjustable Anti-Cross Conduction Delay section...................................................................................................... 22
• Added Table 4 ..................................................................................................................................................................... 28
5 Description (continued)
Using the PMBus protocol, the device margining function, reference voltage, fault limit, UVLO threshold, soft-start
time, turn-on delay, and turn-off delay can be programmed.
In addition, an accurate measurement system is implemented to monitor the output voltages, currents and
temperatures for each channel.
Copyright © 2011–2017, Texas Instruments Incorporated
Product Folder Links: TPS40422
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