Driverless Controller. TPS40428 Datasheet

TPS40428 Controller. Datasheet pdf. Equivalent

TPS40428 Datasheet
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Part TPS40428
Description Synchronous Buck Driverless Controller
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Texas Instruments TPS40428
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TPS40428
SLUSBV0A – MAY 2014 – REVISED JULY 2014
TPS40428 Dual Output, 2-Phase, Stackable PMBus™ Synchronous Buck Driverless
Controller with Adaptive Voltage Scaling (AVS) Bus
1 Features
1 Smart Power Mode in Factory Default (Compatible
with TI Smart Power Stage CSD95378B and Pin-
for-Pin Equivalent to TPS40425 – Non-Smart
Power Mode in Factory Default)
• Single Supply Operation: 4.5 V to 20 V
• VOUT from 0.6 V
• Dual or Multi-Phase Synchronous Buck Controller
• Individual High-Speed AVS Interface
• Fast Transient Response
• Stackable up to Four Phases
– 2-, 3-, or 4-Phase Interleaved Phase Shifts
– Accurate Current Sharing
• PMBus Interface Capability
– Margining Up/Down with 2-mV Step
– Programmable Fault Limit and Response
– ±0.8% VOUT
– Accuracy Current Monitoring
– ±3°C External Temperature Monitoring In
Smart Power Mode
– Programmable UVLO ON/OFF Thresholds
– Programmable Soft-Start Time, Turn-On
Delay, and Turn-Off Delay
• On-Chip Non-Volatile Memory (NVM) to Store
Custom Configurations
• 0.6-V Reference Voltage with 0.5% Accuracy from
–40°C to 125°C
• Programmable ƒSW from 200 kHz to 1.5 MHz
• Supports Pre-biased Output
• Differential Remote Sensing
• Synchronization to an Extermal Clock
• OC/OV/UV/OT Fault Protection
• 40-Pin, 6 mm × 6 mm, QFN Package
2 Applications
• Wireless Infrastructure
• Switcher/Router Networking/Server/Storage
3 Description
The TPS40428 device is a PMBus, synchronous
buck, driverless controller. It operates in smart power
mode with factory default settings, and it can operate
in non-smart power mode after PMBus programing
and power reboot. It can be configured for dual-
output or 2-phase operation. It is also stackable up to
4 phases to support load current as high as 120 A.
Interleaved phase shift for 2-. 3-, or 4-phases reduce
the input and output ripples therefore reducing input
and output capacitance.
The wide input voltage range can support 5-V and
12-V intermediate supply buses. The 0.5% reference
voltage satisfies the need of precision voltage to the
modern ASICs.
Using the PMBus standard, the TPS40428 device
can program reference voltage, fault limit, UVLO
threshold, soft-start time and turn-on and turn-off
delay.
In addition, the device implements an accurate
measurement system to monitor the output voltages,
currents and temperatures for individual channels.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS40428
RHA (40)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application (Dual Output)
GND
VOUT1
GND
Smart Power Stage
VIN
SW
GND
PWM
TAO
IOUT
REFIN
TPS40428
PWM1
TSNS1
CS1P
CS1N
PWM2
TSNS2
CS2P
CS2N
ISH1
FLT1
{Remote SNS to VOUT1
DIFFO1
VSNS1
GSNS1
ISH2
FLT2
VSNS2
GSNS2
FB1
COMP1
FB2
COMP2
Smart Power Stage
PWM
TAO
IOUT
REFIN
VIN
SW
GND
VIN
GND
GND
VOUT2
VOUT2
GND
PG1
PG2
CNTL1
SYNC
CNTL2
VDD
VIN
{PMBus Interface
PHSET
BP3
PMBDATA AGND
PMBCLK
SMBALERT BP5
RT PGND
ADDR0 AVSDATA
ADDR1 AVSCLK
}High-Speed AVSBUS
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments TPS40428
TPS40428
SLUSBV0A – MAY 2014 – REVISED JULY 2014
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings ...................................................... 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics ............................................ 10
7 Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 23
7.5 Programming........................................................... 24
7.6 Register Maps ......................................................... 29
8 Applications and Implementation ...................... 71
8.1 Application Information............................................ 71
8.2 Typical Application .................................................. 71
9 Power Supply Recommendations...................... 80
10 Layout................................................................... 80
10.1 Layout Guidelines ................................................. 80
10.2 Layout Example .................................................... 81
11 Device and Documentation Support ................. 82
11.1 Development Support ........................................... 82
11.2 Trademarks ........................................................... 83
11.3 Electrostatic Discharge Caution ............................ 83
11.4 Glossary ................................................................ 83
12 Mechanical, Packaging, and Orderable
Information ........................................................... 84
4 Revision History
Changes from Original (MAY 2014) to Revision A
Page
• Updated Pin Functions table .................................................................................................................................................. 3
• Updated notes and conditions in Electrical Characteristics table. No updates to specifications. .......................................... 5
• Added clarity to Table 4 ....................................................................................................................................................... 26
• Added clarity to Table 5 ....................................................................................................................................................... 27
• Added clarity to Table 6 ....................................................................................................................................................... 29
• Updated (E0h) MFR_SPECIFIC_16 (COMM_EEPROM_SPARE) section ......................................................................... 61
2 Submit Documentation Feedback
Product Folder Links: TPS40428
Copyright © 2014, Texas Instruments Incorporated



Texas Instruments TPS40428
www.ti.com
5 Pin Configuration and Functions
RHA PACKAGE
40 PINS
(TOP VIEW)
TPS40428
SLUSBV0A – MAY 2014 – REVISED JULY 2014
40 39 38 37 36 35 34 33 32 31
SYNC 1
30 ISH1
PHSET 2
29 PG1
CNTL1 3
28 PWM1
CNTL2 4
27 PGND
SMBALERT 5
PMBDATA 6
TPS40428
26 BP3
25 BP5
PMBCLK 7
AGND 8
Thermal Pad
24 VDD
23 PWM2
AVSDATA 9
22 PG2
AVSCLK 10
21 ISH2
11 12 13 14 15 16 17 18 19 20
PIN
NAME
ADDR1
ADDR0
AGND
AVSCLK
AVSDATA
NO.
11
12
8
10
9
BP3 26
BP5 25
CNTL1
3
CNTL2
COMP1
COMP2
CS1N
CS1P
CS2N
CS2P
DIFFO1
FB1
4
36
15
33
32
18
19
39
35
Pin Functions
I/O DESCRIPTION
I High order address pin for PMBus device. Connect a resistor to AGND (see Table 3).
I Low order address pin for PMBus device. Connect a resistor to AGND (see Table 3).
— Analog ground pin, used for analog signal. Connect to thermal pad directly.
I AVS clock
I AVS data
O
3.3-V bias power for logic. A low-ESR ceramic capacitor with a value of 0.33 µF or greater should be
connected closely from this pin or to AGND. The maximum suggested capacitor value is 10 µF.
O
Output bypass for the internal regulator. A low-ESR ceramic capacitor of 1 µF or greater should be
connected closely from this pin to PGND pin. The maximum suggested capacitor value is 10 µF.
I
Logic level input which starts or stops channel 1. An internal 6-µA current source pulls VCNTL1 up to VBP5
when the pin is floating.
I
Logic level input which starts or stops channel 2. An internal 6-µA current source pulls VCNTL2 up to VBP5
when the pin is floating.
O Output of the error amplifier 1 and connection node for loop feedback components
O Output of the error amplifier 2 and connection node for loop feedback components
I
Negative pin of current sense amplifier for channel 1. An internal, 4-kΩ resistor pulls CS1N to 1.24 V during
smart power mode operation to provide a bias voltage required by smart power stage.
I Positive pin of current sense amplifier for channel 1
I
Negative pin of current sense amplifier for channel 2. An internal, 4-kΩ resistor pulls CS2N to 1.24 V during
smart power mode operation to provide a bias voltage required by smart power stage.
I Positive pin of current sense amplifier for channel 2
O Remote Sense Amplifier Output for channel 1
I
Inverting input to the error amplifier 1. In normal operation, the voltage on this pin is equal to the internal
reference voltage. Connect the FB1 pin to the BP5 pin to set the channel as slave channel.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS40428
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