Buck Controller. TPS40400 Datasheet

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TPS40400 Datasheet
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Part TPS40400
Description 3-V to 20-V PMBus Synchronous Buck Controller
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TPS40400
SLUS930D – APRIL 2011 – REVISED NOVEMBER 2016
TPS40400 3-V to 20-V PMBus Synchronous Buck Controller
1 Features
1 Input Operating Voltage Range: 3 V to 20 V
• PMBus Enabled Analog Controller
• Reference 600 mV ± 1%
• Remote Voltage Sense Amplifier
• Internal 6-V Regulator and 6-V Gate Drive
• Programmable Overcurrent Protection
• Inductor Resistance or Series Resistance Used
for Current Sensing
• Programmable Switching Frequency: 200 kHz to 2
MHz
• Powergood Indicator
• Thermal Shutdown
• Programmable Soft-Start
• Internal Bootstrap Diode
• Prebias Output Safe
• 24-Pin QFN Package
2 Applications
• Smart Power Systems
• Power Supply Modules
• Communications Equipment
• Computing Equipment
3 Description
The TPS40400 is a cost-optimized flexible
synchronous buck controller that operates from a
nominal 3-V to 20-V supply. This controller is an
analog PWM controller that allows programming and
monitoring through the PMBus™ interface. Flexible
features found on this device include programmable
soft-start time, programmable short circuit limit, and
programmable undervoltage lockout (UVLO).
An adaptive anti-cross conduction scheme is used to
prevent shoot through current in the power FETs.
Gate drive voltage is 6 V to better enhance the power
FETs for reduced losses. Short circuit detection
occurs by sensing the voltage drop across the
inductor or across a resistor placed in series with the
inductor. A PMBus programmable threshold is
compared to this voltage and is used to detect
overcurrent. When the overcurrent threshold is
reached, a pulse by pulse current limit scheme is
used to limit the current to acceptable levels. If the
overcurrent condition persists for more than 7 clock
cycles of the converter, a fault condition is declared
and the converter shuts down and goes into either a
hiccup restart mode or latches off. The behavior can
be selected through the PMBus interface. Other
PMBus interface features include programmable
operating frequency, soft-start time, overvoltage and
undervoltage thresholds and the response to those
events, output voltage change including margining as
well as status monitoring.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS40400
VQFN (24)
3.50 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
SMBALRT
DATA
CLK
CNTL
PGOOD
SYNC
TRACK
1 CLK
DATA 24
2 CNTL
SMBALRT 23
3 PGOOD
ADDR1 22
4 SYNC
ADDR0 21
5 TRACK
VDD 20
6 COMP
7 FB
TPS40400
HDRV 19
BOOT 18
8 DIFFO
SW 17
9 VSNS+
10 VSNS–
11 ISNS–
ISNS+
12
SGND
25
LDRV 16
GND 15
BP6 14
BP3
13
VIN
1
VOUT+
VOUT
SNS+
SNS–
UDG-09073
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments TPS40400
TPS40400
SLUS930D – APRIL 2011 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics .......................................... 5
6.6 Switching Characteristics .......................................... 9
6.7 Dissipation Ratings ................................................... 9
6.8 Typical Characteristics ............................................ 10
7 Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 23
7.5 Programming........................................................... 24
7.6 Register Maps ........................................................ 26
8 Application and Implementation ........................ 56
8.1 Application Information............................................ 56
8.2 Typical Applications ................................................ 57
8.3 Initialization Setup ................................................... 69
9 Power Supply Recommendations...................... 71
10 Layout................................................................... 71
10.1 Layout Guidelines ................................................. 71
10.2 Layout Examples................................................... 72
10.3 Thermal Considerations ........................................ 73
11 Device and Documentation Support ................. 74
11.1 Device Support...................................................... 74
11.2 Community Resources.......................................... 74
11.3 Trademarks ........................................................... 74
11.4 Electrostatic Discharge Caution ............................ 74
11.5 Glossary ................................................................ 74
12 Mechanical, Packaging, and Orderable
Information ........................................................... 74
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2015) to Revision D
Page
• Changed VQFN (24) package dimensions from: 3.50 mm × 3.50 mm to: 3.50 mm × 5.50 mm ........................................... 1
Changes from Revision B (September 2015) to Revision C
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Original (March 2012) to Revision A
Page
• Corrected default values in ON_OFF_CONFIG register map ............................................................................................. 27
• Added Design Example 1 .................................................................................................................................................... 57
• Added Design Example 2 ..................................................................................................................................................... 66
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Product Folder Links: TPS40400
Copyright © 2011–2016, Texas Instruments Incorporated



Texas Instruments TPS40400
www.ti.com
5 Pin Configuration and Functions
TPS40400
SLUS930D – APRIL 2011 – REVISED NOVEMBER 2016
PIN
NAME
NO.
ADDR0
21
ADDR1
22
BOOT
18
BP3 13
BP6
CLK
CNTL
COMP
DATA
DIFFO
FB
14
1
2
6
24
8
7
GND
HDRV
ISNS–
ISNS+
LDRV
15
19
11
12
16
RHL Package
24-Pin VQFN
Bottom View
DATA
CLK
SMBALRT
ADDR1
ADDR0
VDD
HDRV
BOOT
SW
LDRV
GND
BP6
23 24
12
22 3
21 4
20 5
19 TPS40400
6
18 7
17 Thermal Pad 8
SGND
16 9
15 10
14 13
12 11
CNTL
PGOOD
SYNC
TRACK
COMP
FB
DIFFO
VSNS+
VSNS–
ISNS–
BP3 ISNS+
I/O (1)
I
I
I
O
O
I
I
O
I/O
O
I
O
I
I
O
Pin Functions
DESCRIPTION
Low-order address pin for PMBus address configuration. One of eight resistor values must be connected
from this pin to SGND to select the low-order octal digit in the PMBus address.
High-order address pin for PMBus address configuration. One of eight resistor values must be
connected from this pin to SGND to select the high-order octal digit in the PMBus address.
Gate drive voltage for the high-side, N-channel MOSFET. A capacitor (100-nF) typical must be
connected between this pin and SW.
Bypass pin for the internal regulator that supplies power to the internal controls of the device. Normal
regulation voltage is 3.3 V. Connect a capacitor with a value of 100-nF or larger from this pin to GND.
Bypass pin for the internal regulator that supplies power to the gate drivers. Normal regulation voltage is
6.5 V. Connect a capacitor with a value of 1-μF or larger from this pin to GND.
Clock input for the PMBus interface
Logic level input that controls the start-up and shutdown of the converter. PMBus options determine
exact functionality.
Output of the error amplifier. Used for control loop compensation.
Data I/O for the PMBus interface
Output of the unity gain remote voltage sense amplifier. Typically connected to the voltage divider on FB
Inverting input to the error amplifier. A voltage divider is connected to from the DIFFO pin to the FB pin
to sense the output voltage.
Common connection for the device. This pin should connect to the thermal pad under the device
package and to the power stage ground, preferably close to the source of the low-side or rectifier
MOSFET. Connections should be arranged so that no high-power level currents flow across the pad
connected to the thermal pad on the underside of the device.
Gate drive signal to the high-side MOSFET
Inverting input to the current sense amplifier
Noninverting input to the current sense amplifier
Output used to drive the gate of the low-side or rectifier MOSFET.
(1) I = Input, O = Output, P = Supply, G = Ground
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS40400
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