Audio Codec. TLV320AIC3263 Datasheet

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TLV320AIC3263 Datasheet
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Part TLV320AIC3263
Description Ultra Low Power Stereo Audio Codec
Feature TLV320AIC3263; TLV320AIC3263 www.ti.com SLAS923 – JUNE 2013 Ultra Low Power Stereo Audio Codec With miniDSP, Dir.
Manufacture etcTI
Datasheet
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Texas Instruments TLV320AIC3263
TLV320AIC3263
www.ti.com
SLAS923 – JUNE 2013
Ultra Low Power Stereo Audio Codec With miniDSP, DirectPath Headphone, and Class-D
Speaker Amplifier
Check for Samples: TLV320AIC3263
FEATURES
1
2 Stereo Audio DAC with 101dB SNR
• 2.7mW Stereo 48kHz DAC Playback
• Stereo Audio ADC with 93dB SNR
• 6.1mW Stereo 48kHz ADC Record
• 8-192kHz Playback and Record
• 30mW DirectPathTM Headphone Driver
Eliminates Large Output DC-Blocking
Capacitors
• 128mW Differential Receiver Output Driver
• Class-D Speaker Driver
– 1.7 W (8Ω , 5.5V, 10% THDN)
– 1.4 W (8Ω , 5.5V, 1% THDN)
• Stereo Line Outputs
• PowerTune™ - Adjusts Power versus SNR
• Extensive Signal Processing Options
• Eight Single-Ended or 4 Fully-Differential
Analog Inputs
• Analog Microphone Inputs, and Up to 4
Simultaneous Digital Microphone Channels
• Low Power Analog Bypass Mode
• Fully-programmable Enhanced miniDSP with
PurePathTM Studio Support
– Extensive Algorithm Support for Voice and
Audio Applications
• Three Independent Digital Audio Serial
Interfaces with Separate I/O Power Voltages
– TDM and mono PCM support on all Audio
Serial Interfaces
– 8-channel Input and Output on Audio Serial
Interface 1
• Programmable PLL, plus Low-Frequency
Clocking
• Programmable 12-Bit SAR ADC
• SPI and I2C Control Interfaces
• 4.81 mm x 4.81 mm x 0.625 mm 81-Ball WCSP
(DSBGA) Package
AIC3262
APPLICATIONS
• Mobile Handsets
• Tablets, eBooks
• Portable Navigation Devices (PND)
• Portable Media Player (PMP)
• Portable Gaming Systems
• Portable Computing
• Active Noise Cancellation (ANC)
• Speaker Protection
• Advanced DSP algorithms
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerTune is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated



Texas Instruments TLV320AIC3263
TLV320AIC3263
SLAS923 – JUNE 2013
www.ti.com
DESCRIPTION
The TLV320AIC3263 (also referred to as the AIC3263) is a flexible, highly-integrated, low-power, low-voltage
stereo audio codec. The AIC3263 features four digital microphone inputs, plus programmable outputs,
PowerTune capabilities, enhanced fully-programmable miniDSP, predefined and parameterizable signal
processing blocks, integrated PLL, and flexible digital audio interfaces. Extensive register-based control of power,
input and output channel configuration, gains, effects, pin-multiplexing and clocks are included, allowing the
device to be precisely targeted to its application.
VREF_SAR
VBAT
IN1L/AUX1
IN2L
IN3L
IN4L
IN4R
IN3R
IN2R
IN1R/AUX2
SPI_SELECT
RESET
MICDET
MICBIAS
MICBIAS_EXT
VREF_AUDIO
TEMP
SENSOR
–12, –6, 0dB
–12, –6, 0dB
–12, –6, 0dB
–6 dB
–6 dB
–12, –6, 0dB
–12, –6, 0dB
–12, –6, 0dB
VBAT
IN1L/AUX1
IN1R/AUX2
TEMP
-6dB
SAR
ADC
Int.
Ref.
-12, -6, 0dB
0=47.5dB
(0.5-dB Steps)
0=47.5dB
(0.5-dB Steps)
AGC
DRC Vol. Ctrl.
Left
ADC
tPL
ADC
Signal
Proc.
–36...0dB
Gain Adj.
MAL
DAC
Signal
Proc.
Left +
DAC –
–36...0dB
miniDSP
Dig Mixer
Volume
MAR
Audio
Interface
miniDSP
ASRC
Dig Mixer
Volume
Right
ADC
Gain Adj.
ADC
tPR Signal
Proc.
AGC
DAC
Signal
Proc.
Right –
DAC +
DRC
Vol. Ctrl.
-12, -6, 0dB
LOL
-78...0dB
IN1L
-78...0dB
LOR
-78...0dB
IN1R
-78...0dB
-6...29dB
(1-dB Steps)
6...30dB
(6-dB Steps)
LOL
-78...0dB
RIGHT_
CH_IN
LOR
-78...0dB
-6...14dB
(1-dB Steps)
RECP
RECM
SPKP
SPKM
HPL
-78...0dB
LOL
HPVSS_SENSE
LOR
-78...0dB
HPR
-6...14dB
(1-dB Steps)
-6dB
Low Freq
Clocking
Mic
Bias
Ref
Detection
Charge
Pump
Supplies
SPI / I2C
Control Block
PLL
Digital Interrupt
Mic. (x4) Ctrl
Tertiary Secondary Primary
Audio IF Audio IF Audio Interface
Pin Muxing / Clock Routing
Figure 1. Simplified Block Diagram
2 Submit Documentation Feedback
Product Folder Links: TLV320AIC3263
Copyright © 2013, Texas Instruments Incorporated



Texas Instruments TLV320AIC3263
TLV320AIC3263
www.ti.com
SLAS923 – JUNE 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The TLV320AIC3263 features two fully-programmable miniDSP cores that support application-specific algorithms
in the record and/or the playback path of the device. The miniDSP cores are fully software programmable.
Targeted miniDSP algorithms, such as active noise cancellation, acoustic echo cancellation or advanced DSP
filtering are loaded into the device after power-up.
Combined with the advanced PowerTune technology, the device can execute operations from 8kHz mono voice
playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC3263 covers operations from 8kHz mono to 192kHz stereo recording, and
contains programmable input channel configurations which cover single-ended and differential setups, as well as
floating or mixing input signals. It also provides a digitally-controlled stereo microphone preamplifier and
integrated microphone bias. One application of the digital signal processing blocks is removable of audible noise
that may be introduced by mechanical coupling, such as optical zooming in a digital camera. The record path can
also be configured for up to two stereo (such as up to 4) simultaneous digital microphone Pulse Density
Modulation (PDM) interfaces typically used at 64Fs or 128Fs.
The playback path offers signal processing blocks for filtering and effects; headphone, line, receiver, and Class-D
speaker output; flexible mixing of DAC; and analog input signals as well as programmable volume controls. The
playback path contains two high-power DirectPathTM headphone output drivers which eliminate the need for ac
coupling capacitors. A built in charge pump generates the negative supply for the ground centered headphone
drivers. These headphone output drivers can be configured in multiple ways, including stereo, and mono BTL. In
addition, playback audio can be routed to an integrated Class-D speaker driver or a differential receiver amplifier.
The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-
off. Mobile applications frequently have multiple use cases requiring very low-power operation while being used
in a mobile environment. When used in a docked environment power consumption typically is less of a concern
while lowest possible noise is important. With PowerTune the TLV320AIC3263 can address both cases.
The required internal clock of the TLV320AIC3263 can be derived from multiple sources, including the MCLK pin,
the BCLK1 pin, the BCLK2 pin, several general purpose I/O pins or the output of the internal PLL, where the
input to the PLL again can be derived from similar pins. Although using the internal fractional PLL ensures the
availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is highly
programmable and can accept available input clocks in the range of 512kHz to 50MHz. To enable even lower
clock frequencies, an integrated low-frequency clock multiplier can also be used as an input to the PLL.
The TLV320AIC3263 has a 12-bit SAR ADC converter that supports system voltage measurements. These
system voltage measurements can be sourced from three dedicated analog inputs (IN1L/AUX1, IN1R/AUX2, or
VBAT pins), or, alternatively, an on-chip temperature sensor that can be read by the SAR ADC.
The device also features three full Digital Audio Serial Interfaces, each supporting I2S, DSP/TDM, RJF, LJF, and
mono PCM formats. This enables three simultaneous digital playback and record paths to three independent
digital audio buses or chips. Additionally, the general purpose interrupt pins can be used to connect to a fourth
digital audio bus, allowing the end system to easily switch in this fourth audio bus to one of the three Digital
Audio Serial Interfaces. Each of the three Digital Audio Serial Interfaces can be run using separate power
voltages to enable easy integration with separate chips with different I/O voltages.
The device is available in the 4.81 mm x 4.81 mm x 0.625 mm 81-Ball WCSP (DSBGA) Package.
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3263
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