UCC27528-Q1 Logic Datasheet

UCC27528-Q1 Datasheet, PDF, Equivalent


Part Number

UCC27528-Q1

Description

CMOS Input Threshold Logic

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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UCC27528-Q1
SNVSA89A – DECEMBER 2014 – REVISED MAY 2015
UCC27528-Q1 Dual 5-A High-Speed Low-Side Gate Driver Based on
CMOS Input Threshold Logic
1 Features
1 Qualified for Automotive Applications
• AEC-Q100 Device Temperature Grade 1
• Industry-Standard Pin Out
• Two Independent Gate-Drive Channels
• 5-A Peak Source and Sink Drive Current
• CMOS Input Logic Threshold
(Function of Supply Voltage on VDD Pins)
• Hysteretic Logic Thresholds for High Noise
Immunity
• Independent Enable Function for Each Output
• Inputs and Enable Pin Voltage Levels Not
Restricted by VDD Pin Bias Supply Voltage
• 4.5-V to 18-V Single Supply Range
• Outputs Held Low During VDD UVLO (Ensures
Glitch-Free Operation at Power Up and Power
Down)
• Fast Propagation Delays (17-ns Typical)
• Fast Rise and Fall Times (7-ns and 6-ns Typical)
• 1-ns Typical Delay Matching Between 2 Channels
• Outputs Held in Low When Inputs Floating
• SOIC-8 Package
• Operating Temperature Range of –40°C to 140°C
• –5-V Negative Voltage Handling Capability on
Input Pins
2 Applications
• Automotive
• Switch-Mode Power Supplies
• DC-to-DC Converters
• Motor Control, Solar Power
• Gate Drive for Emerging Wideband Gap Power
Devices Such as GaN
3 Description
The UCC27528-Q1 device is a dual-channel, high-
speed, low-side gate driver capable of effectively
driving MOSFET and IGBT power switches. Using a
design that inherently minimizes shoot-through
current, the UCC27528-Q1 device can deliver high-
peak current pulses of up to 5-A source and 5-A sink
into capacitive loads along with rail-to-rail drive
capability and extremely small propagation delay of
17 ns (typical). In addition, the drivers feature
matched internal propagation delays between the two
channels which are very well suited for applications
requiring dual-gate drives with critical timing, such as
synchronous rectifiers. The input pin thresholds are
based on CMOS logic, which is a function of the VDD
supply voltage. Wide hysteresis between the high and
low thresholds offers excellent noise immunity. The
enable pins are based on TTL and CMOS compatible
logic, independent of the VDD supply voltage.
Device Information(1)
PART NUMBER PACKAGE
BODY SIZE (NOM)
UCC27528-Q1
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Dual Non-Inverting Inputs
UCC27528-Q1
ENA 1
8 ENB
INA 2
7 OUTA
GND 3
6 VDD
INB 4
5 OUTB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC27528-Q1
UCC27528-Q1
SNVSA89A – DECEMBER 2014 – REVISED MAY 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Switching Characteristics .......................................... 5
7.7 Typical Characteristics .............................................. 7
8 Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 15
9 Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 21
11.3 Thermal Considerations ........................................ 21
12 Device and Documentation Support ................. 21
12.1 Trademarks ........................................................... 21
12.2 Electrostatic Discharge Caution ............................ 21
12.3 Glossary ................................................................ 21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Original (December 2015) to Revision A
Page
• Changed device status from Product Preview to Production Data ....................................................................................... 1
2 Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: UCC27528-Q1


Features Product Folder Sample & Buy Technical Documents Tools & Software Support & Community UCC27528-Q1 SNVSA89A – DEC EMBER 2014 – REVISED MAY 2015 UCC2752 8-Q1 Dual 5-A High-Speed Low-Side Gate Driver Based on CMOS Input Threshold Lo gic 1 Features •1 Qualified for Auto motive Applications • AEC-Q100 Device Temperature Grade 1 • Industry-Stand ard Pin Out • Two Independent Gate-Dr ive Channels • 5-A Peak Source and Si nk Drive Current • CMOS Input Logic T hreshold (Function of Supply Voltage on VDD Pins) • Hysteretic Logic Thresho lds for High Noise Immunity • Indepen dent Enable Function for Each Output Inputs and Enable Pin Voltage Levels Not Restricted by VDD Pin Bias Supply V oltage • 4.5-V to 18-V Single Supply Range • Outputs Held Low During VDD U VLO (Ensures Glitch-Free Operation at P ower Up and Power Down) • Fast Propag ation Delays (17-ns Typical) • Fast R ise and Fall Times (7-ns and 6-ns Typic al) • 1-ns Typical Delay Matching Between 2 Channels • Outputs Held in Low When Inputs Floati.
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