Cable Driver. LMH0040 Datasheet

LMH0040 Driver. Datasheet pdf. Equivalent

LMH0040 Datasheet
Recommendation LMH0040 Datasheet
Part LMH0040
Description DVB-ASI SDI Serializer and Cable Driver
Feature LMH0040; www.ti.com LMH0040, LMH0050 LMH0070, LMH0340 SNLS271I – APRIL 2007 – REVISED APRIL 2013 3 Gbps, HD.
Manufacture etcTI
Datasheet
Download LMH0040 Datasheet





Texas Instruments LMH0040
www.ti.com
LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I – APRIL 2007 – REVISED APRIL 2013
3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface
Check for Samples: LMH0040, LMH0050, LMH0070, LMH0340
FEATURES
1
2 LVDS Interface to Host FPGA
• No External VCO or Clock Ref Required
• Integrated Variable Output Cable Driver
• 3.3V SMBus Configuration Interface
• Integrated TXCLK PLL Cleans Clock Noise
• Small 48-Pin WQFN Package
• Industrial Temperature range: -40°C to 85°C
APPLICATIONS
• SDI Unterfaces for:
– Video Cameras
– DVRs
– Video Switchers
– Video Editing Systems
KEY SPECIFICATIONS
• Output Compliant With SMPTE 424M, SMPTE
292M, SMPTE 259M-C and DVB-ASI (See
Table 1)
• Typical Power Dissipation: 440 mW
• 30 ps Typical Output Jitter (HD, 3G)
DESCRIPTION
The LMH0340/0040/0070/0050 SDI Serializers are
part of TI’s family of FPGA-Attach SER/DES products
supporting 5-bit LVDS interfaces with FPGAs. An
FPGA Host will format data with supplied IP such that
the output of the LMH0340 is compliant with the
requirements of DVB-ASI, SMPTE 259M-C, SMPTE
292M and SMPTE 424M standards. See Table 1 for
details on which Standards are supported per device.
The interface between the SER (Serializer) and the
FPGA consists of a 5 bit wide LVDS data bus, an
LVDS clock and an SMBus interface. The
LMH0340/0040/0070 SER devices include an
integrated cable driver which is fully compliant with all
of the SMPTE specifications listed above. The
LMH0050 has a CML output driver that can drive a
differential transmission line or interface to a cable
driver.
The FPGA-Attach SER/DES family is supported by a
suite of IP which allows the design engineer to
quickly develop video applications using the
SER/DES products. The SER is packaged in a
physically small 48-pin WQFN package.
General Block Diagram
SDA
SCK
SMB_CS
RESET
DVB_ASI
SMBus
Control
LOCK
GPIO[2:0]
TX4
TX3
TX2
TX1
TX0
TXCLK
LVDS Receivers
PLL Clock
Generation
TXOUT
SMPTE Cable Driver
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated



Texas Instruments LMH0040
LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I – APRIL 2007 – REVISED APRIL 2013
Connection Diagram
VDD3V3 1
RSVH_H 2
GPIO_0 3
GPIO_1 4
RSVD_H 5
DVB_ASI 6
VDD2V5 7
GND 8
GND 9
GND 10
GPIO_2 11
GND 12
LMH0340,
LMH0070,
LMH0040,
LMH0050,
TOP VIEW
(not to scale)
48-pin WQFN Package
DAP = GND
www.ti.com
36 VDD3V3
35 VDD2V5
34 SMB_CS
33 SCK
32 SDA
31 LOCK
30 RESET
29 GND
28 VDDPLL
27 LF_CP
26 LF_REF
25 VDD2V5
Figure 1. Connection Diagram for 48L WQFN Package
2 Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340



Texas Instruments LMH0040
www.ti.com
Pin Name
Type
LVDS Input Interface
TX[4:0]+
TX[4:0]-
Input, LVDS
TXCLK+
TXCLK-
Input, LVDS
Serial Output Interface
TXOUT+
Output, CML
TXOUT-
Output, CML
SMBus Interface
SDA
SCK
SMB_CS
I/O, LVCMOS
Input, LVCMOS
Input, LVCMOS
Control and Configuration Pins
RESET
Input, LVCMOS
LOCK
Output, LVCMOS
DVB_ASI
Input, LVCMOS
GPIO[2:0]
RSVD_H
Analog Inputs
RSET
I/O, LVCMOS
Input, LVCMOS
Input, analog
LF_CP
Input, analog
LF_REF
Input, analog
DNC
Power Supply and Ground
VDD3V3
VDDPLL
VDD2V5
GND
Power
Power
Power
Ground
Device
LMH0340
LMH0040
LMH0070
LMH0050
SMPTE 424M
Support (3G)
X
PIN DESCRIPTIONS
Description
LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I – APRIL 2007 – REVISED APRIL 2013
LVDS Data Input Pins
Five channel wide DDR interface. Internal 100termination.
LVDS Clock Input Pins
DDR Interface. Internal 100termination.
Serial Digital Interface Output Pin
Non-Inverting Output
Serial Digital Interface Output Pin
Inverting Output
SMBus Data I/O Pin
SMBus Clock Input Pin
SMBus Chip Select Input Pin
Device is selected when High.
Reset Input Pin
H = normal mode
L = device in RESET
PLL LOCK Status Output
H = unlock condition
L = Device is Locked
DVB_ASI Select Input
H = DVB_ASI Mode enabled
L = Normal Mode enabled
General Purpose Input / Output
Software configurable I/O pins.
Configuration Input – Must tie High
Pull High via 5 kresistor to VDD3V3
Serial Output Amplitude Control
Resistor connected from this pin to ground to set the signal amplitude. Nominally
8.06kfor 800mV output (SMPTE).
Loop Filter Connection
Loop Filter Reference
Do Not Connect – Leave Open
3.3V Power Supply connection
3.3V PLL Power Supply connection
2.5V Power Supply connection
Ground connection – The DAP (large center pad) is the primary GND connection for
the device and must be connected to Ground along with the GND pins.
Table 1. Feature Table
SMPTE 292M
Support (HD)
X
X
X
SMPTE 259M
Support (SD)
X
X
X
X
DVB-ASI
Support
X
X
X
X
SMPTE compliant
Cable Driver
X
X
X
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340
3





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