DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP
SN74HC74-Q1
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCLS577A − MARCH 2004 − REVISED APRIL 20...
Description
SN74HC74-Q1
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCLS577A − MARCH 2004 − REVISED APRIL 2008
D Qualified for Automotive Applications D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 15 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max
D OR PW PACKAGE (TOP VIEW)
1CLR 1D
1CLK 1PRE
1Q 1Q GND
1 2 3 4 5 6 7
14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q
description/ordering information
The SN74HC74 device contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION{
TA
PACKAGE‡
ORDERABLE PART NUMBER
TOP-SIDE MARKING
−40°C to 125°C
SOIC − D TSSOP − PW
Reel of 2500 Reel of 2000
SN74HC74QDRQ1 SN74HC74QPWRQ1
HC74Q HC74Q
† For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or see the TI web site at http://www.ti.com. ‡ Package draw...
Similar Datasheet