SN74HC7002 GATES Datasheet

SN74HC7002 Datasheet, PDF, Equivalent


Part Number

SN74HC7002

Description

QUADRUPLE POSITIVE-NOR GATES

Manufacture

etcTI

Total Page 14 Pages
Datasheet
Download SN74HC7002 Datasheet


SN74HC7002
D Wide Operating Voltage Range of 2 V to 6 V
D Typical tpd = 14 ns
D Low Power Consumption, 20-µA Max ICC
D Low Input Current of 1 µA Max
D Operation From Very Slow Input
Transitions
D Temperature-Compensated Threshold
Levels
D High Noise Immunity
description/ordering information
In these devices, each circuit functions as a
quadruple NOR gate. They perform the Boolean
function Y = A B or Y = A + B in positive logic.
However, because of the Schmitt action, the
inputs have different input threshold levels for
positive- and negative-going signals.
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
SN54HC7002, SN74HC7002
QUADRUPLE POSITIVEĆNOR GATES
WITH SCHMITTĆTRIGGER INPUTS
SCLS033F − MARCH 1984 − REVISED NOVEMBER 2004
SN54HC7002 . . . J OR W PACKAGE
SN74HC7002 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
SN54HC7002 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
1Y 4
18 4A
NC 5
17 NC
2A 6
16 4Y
NC 7
15 NC
2B 8
14 3B
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC7002N
SN74HC7002N
Tube of 50
SN74HC7002D
−40°C to 85°C
SOIC − D
SOP − NS
Reel of 2500
Reel of 250
Reel of 2000
SN74HC7002DR
SN74HC7002DT
SN74HC7002NSR
HC7002
HC7002
Tube of 90
SN74HC7002PW
TSSOP − PW
Reel of 2000
Reel of 250
SN74HC7002PWR
SN74HC7002PWT
HC7002
CDIP − J
Tube of 25
SNJ54HC7002J
SNJ54HC7002J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC7002W
SNJ54HC7002W
LCCC - FK
Tube of 55
SNJ54HC7002FK SNJ54HC7002FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
1

SN74HC7002
SN54HC7002, SN74HC7002
QUADRUPLE POSITIVEĆNOR GATES
WITH SCHMITTĆTRIGGER INPUTS
SCLS033F − MARCH 1984 − REVISED NOVEMBER 2004
FUNCTION TABLE
(each gate)
INPUTS
AB
OUTPUT
Y
HX
L
XH
L
LL
H
logic diagram (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC7002
MIN NOM MAX
SN74HC7002
UNIT
MIN NOM MAX
VCC Supply voltage
2 5 6 2 5 6V
VI Input voltage
0
VCC
0
VCC V
VO Output voltage
0
VCC
0
VCC V
TA Operating free-air temperature
−55 125 −40
85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D Wide Operating Voltage Range of 2 V to 6 V D Typical tpd = 14 ns D Low Power Consumption, 20-µA Max ICC D Low Input Current of 1 µA Max D Operation From Very Slow Input Transitions D Temperatu re-Compensated Threshold Levels D High Noise Immunity description/ordering inf ormation In these devices, each circuit functions as a quadruple NOR gate. The y perform the Boolean function Y = A B or Y = A + B in positive logic. How ever, because of the Schmitt action, th e inputs have different input threshold levels for positive- and negative-goin g signals. These circuits are temperatu re compensated and can be triggered fro m the slowest of input ramps and still give clean jitter-free output signals. SN54HC7002, SN74HC7002 QUADRUPLE POSIT IVEĆNOR GATES WITH SCHMITTĆTRIGGER IN PUTS SCLS033F − MARCH 1984 − REVISE D NOVEMBER 2004 SN54HC7002 . . . J OR W PACKAGE SN74HC7002 . . . D, N, NS, OR PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2 Y GND 1 2 3 4 5 6 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y SN54HC700.
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