DS125DF111 Retimer Datasheet

DS125DF111 Datasheet, PDF, Equivalent


Part Number

DS125DF111

Description

Multi-Protocol 2-Channel 9.8 - 12.5Gb/s Retimer

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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DS125DF111
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DS125DF111
SNLS450A – JANUARY 2014 – REVISED JUNE 2015
DS125DF111 Multi-Protocol 2-Channel 9.8 - 12.5 Gb/s Retimer
1 Features
1 Pin Compatible Retimer Family
– DS110DF111 with DFE: 8.5 - 11.3 Gbps
– DS125DF111 with DFE: 9.8 - 12.5 Gbps
• Adaptive CTLE: 33 dB Max Boost at 6.25 GHz
• Self Tuning 5-Tap DFE
• Raw Equalized and Retimed Data Loopback
• Adjustable Transmit VOD: 600 to 1300 mVp-p
• Settable Tx De-Emphasis Driver 0 to –12dB
• Low Power Consumption: 220 mW/Channel
• Locks to Half/Quarter/Eighth Data Rates for
Legacy Support
• On-Chip Eye Monitor (EOM), PRBS Generator
• Input Signal Detection, CDR Lock
Detection/Indicator
• Single 3.3-V or 2.5-V Power Supply
• SMBus, EEPROM, or Pin Based Configuration
• 4-mm x 4-mm, 24-Pin WQFN Package
• Operating Temp Range: –40°C to 85°C
2 Applications
• Front Port Optical Interconnects
• SFF-8431
• 10G/1G Ethernet
• CPRI
3 Description
The DS125DF111 is a dual channel (1-lane
bidirectional) retimer with integrated signal
conditioning. The DS125DF111 includes an input
Continuous-Time Linear Equalizer (CTLE), clock and
data recovery (CDR) and transmit driver on each
channel.
The DS125DF111 with its on-chip Decision Feedback
Equalizer (DFE) can enhance the reach and
robustness of long, lossy, cross-talk-impaired high
speed serial links to achieve BER < 1x10–15. For less
demanding applications/interconnects, the DFE can
be switched off and achieve the same BER
performance. The DS125DF111 and DS110DF111
devices are pin-compatible.
Each channel of the DS125DF111 independently
locks to specific serial data at data rates from 9.8 to
12.5 Gbps or to any supported sub-rate of these data
rates. This simplifies system design and lowers
overall cost.
Programmable transmit de-emphasis driver offers
precise settings to meet the SFF-8431 output eye
template. The fully adaptive receive equalization
(CTLE and DFE) enables longer distance
transmission in lossy copper interconnect and
backplanes with multiple connectors. The CDR
function is ideal for use in front port parallel optical
module applications to reset the jitter budget and
retime high speed serial data.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS125DF111
WQFN (24)
4.0 mm × 4.0 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
100nF
100nF
25 MHz
3.3V
1F
0.22F
(2x)
Typical Application
OUTA_P
OUTA_N
DS125DF111
INA_P
INA_N
INB_P
INB_N
REFCLK_IN
VIN
GND
VDD
GND
DAP
OUTB_P
OUTB_N
SDA
SCL
LPF_REF_B
LPF_CP_B
LPF_REF_A
LPF_CP_A
EN_SMB
TX_DIS
VODA/READ_EN
ADDR0/LOCK
ADDR1/VODB/DONE#
100nF
100nF
1k:
22nF
22nF
1k: 1k:
3.3V
2k: 2k:
3.3V
1k:
1k:
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS125DF111
DS125DF111
SNLS450A – JANUARY 2014 – REVISED JUNE 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration And Functions ........................ 3
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information .................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Timing Requirements ................................................ 9
6.7 Typical Characteristics ............................................ 11
7 Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 17
7.5 Programming........................................................... 18
7.6 Register Maps ......................................................... 35
8 Application and Implementation ........................ 44
8.1 Application Information............................................ 44
8.2 Typical Application ................................................. 44
9 Power Supply Recommendations...................... 46
10 Layout................................................................... 47
10.1 Layout Guidelines ................................................. 47
10.2 Layout Example .................................................... 47
11 Device and Documentation Support ................. 48
11.1 Documentation Support ........................................ 48
11.2 Community Resources.......................................... 48
11.3 Trademarks ........................................................... 48
11.4 Electrostatic Discharge Caution ............................ 48
11.5 Glossary ................................................................ 48
12 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (January 2014) to Revision A
Page
• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
2 Submit Documentation Feedback
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Features Product Folder Sample & Buy Technical Documents Tools & Software Support & Community DS125DF111 SNLS450A – JANU ARY 2014 – REVISED JUNE 2015 DS125DF1 11 Multi-Protocol 2-Channel 9.8 - 12.5 Gb/s Retimer 1 Features •1 Pin Compa tible Retimer Family – DS110DF111 wit h DFE: 8.5 - 11.3 Gbps – DS125DF111 w ith DFE: 9.8 - 12.5 Gbps • Adaptive C TLE: 33 dB Max Boost at 6.25 GHz • Se lf Tuning 5-Tap DFE • Raw Equalized a nd Retimed Data Loopback • Adjustable Transmit VOD: 600 to 1300 mVp-p • Se ttable Tx De-Emphasis Driver 0 to –12 dB • Low Power Consumption: 220 mW/Ch annel • Locks to Half/Quarter/Eighth Data Rates for Legacy Support • On-Ch ip Eye Monitor (EOM), PRBS Generator Input Signal Detection, CDR Lock Dete ction/Indicator • Single 3.3-V or 2.5 -V Power Supply • SMBus, EEPROM, or P in Based Configuration • 4-mm x 4-mm, 24-Pin WQFN Package • Operating Temp Range: –40°C to 85°C 2 Application s • Front Port Optical Interconnects • SFF-8431 • 10G/1G Ethernet • CPRI 3 Description The DS125DF111 is.
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