DS125DF410 Retimer Datasheet

DS125DF410 Datasheet, PDF, Equivalent


Part Number

DS125DF410

Description

Low Power Multi-Rate Quad Channel Retimer

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download DS125DF410 Datasheet


DS125DF410
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
DS125DF410
SNLS398H – JANUARY 2012 – REVISED FEBRUARY 2018
DS125DF410 Low Power Multi-Rate Quad Channel Retimer
1 Features
1 Each Channel Independently Locks to Data Rates
from 9.8 to 12.5 Gbps and Submultiples
• Fast Lock Operation Based on Protocol-Select
Mode
• Low Latency (~300ps)
• Adaptive Equalization up to 34-dB Boost at 5 GHz
• Adjustable Transmit VOD: 600 to 1300 mVp-p
• Adjustable Transmit De-emphasis to –15 dB
• Typical Power Dissipation (EQ+DFE+CDR+DE):
180 mW/Channel
• Programmable Output Polarity Inversion
• Input Signal Detection, CDR Lock
Detection/Indicator
• On-Chip Eye Monitor (EOM), PRBS Generator
• Single 2.5-V ± 5% Power Supply
• SMBus/EEPROM Configuration Modes
• Operating Temperature Range of –40 to 85°C
• WQFN 48-Pin 7-mm x 7-mm Package
• Easy Pin Compatible Upgrade Between Repeater
and Retimers
– DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
– DS100DF410 (EQ+DFE+CDR+DE): 10.3125
Gbps
– DS110RT410 (EQ+CDR+DE): 8.5–11.3 Gbps
– DS110DF410 (EQ+DFE+CDR+DE): 8.5–11.3
Gbps
– DS125RT410 (EQ+CDR+DE): 9.8–12.5 Gbps
– DS125DF410 (EQ+DFE+CDR+DE): 9.8–12.5
Gbps
– DS100BR410 (EQ+DE): Up to 10.3125 Gbps
2 Applications
• Front Port SFF 8431 (SFP+) Optical and Direct
Attach Copper
• Backplane Reach Extension, Data Retimer
• Ethernet: 10 GbE, 1 GbE
• CPRI: Line Bit Rate Options 3–7
• Interlaken: All Lane Bit Rates
• InfiniBand
• Other Propriety Data Rates up to 12.5 Gbps
3 Description
The DS125DF410 is four channel retimer with
integrated signal conditioning. The device includes a
fully adaptive Continuous-Time Linear Equalizer
(CTLE), self calibrating 5-tap Decision Feedback
Equalizer (DFE), Clock and Data Recovery (CDR),
and transmit De-Emphasis (DE) driver to enable data
transmission over long, lossy and crosstalk-impaired
highspeed serial links to achieve BER < 1×10-15.
Each channel can independently lock to data rate
from 9.8 to 12.5 Gbps, and associated sub rates (div
by 2, 4 and 8) to support a variety of communication
protocols. A 25 MHz crystal oscillator clock is used to
speed up the CDR lock process. This clock is not
used for training the PLL and does not need to be
synchronous with the serial data.
The programmable settings can be applied using the
SMBus (I2C) interface, or they can be loaded via an
external EEPROM. An on-chip eye monitor and a
PRBS generator allow real-time measurement of
high-speed serial data for system bring-up or field
tuning.
Device Information(1)
PART NUMBER PACKAGE
BODY SIZE (NOM)
DS125DF410
WQFN (48)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Diagram
Switch Fabric
Line Card
DS125DF410
Optical Modules
x4
ASIC
x4
x4
10GbE
CPRI
SFP+ (SFF8431)
ASIC
Interlaken
QSFP
Others
Back
Plane/
Mid
Plane
x4
DS125DF410
Passive Copper
Clean Signal
Noisy Signal
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS125DF410
DS125DF410
SNLS398H – JANUARY 2012 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics .............................................. 8
7 Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
7.5 Programming........................................................... 18
7.6 Register Maps ......................................................... 33
8 Application and Implementation ........................ 50
8.1 Application Information............................................ 50
8.2 Typical Application ................................................. 50
9 Power Supply Recommendations...................... 52
10 Layout................................................................... 53
10.1 Layout Guidelines ................................................. 53
10.2 Layout Example .................................................... 53
11 Device and Documentation Support ................. 54
11.1 Documentation Support ........................................ 54
11.2 Trademarks ........................................................... 54
11.3 Electrostatic Discharge Caution ............................ 54
11.4 Glossary ................................................................ 54
12 Mechanical, Packaging, and Orderable
Information ........................................................... 54
4 Revision History
Changes from Revision G (March 2015) to Revision H
Page
• Added TEMPLOCK parameter ............................................................................................................................................... 7
Changes from Revision F (January 2015) to Revision G
Page
• Updated Register Values in Table 2..................................................................................................................................... 14
• Changed "0" to "1" for Address 1 Bit 7 and changed "1" to "0" for Address 1 Bit 5 in Table 14.......................................... 34
• Updated Descriptions for Address 2 in Table 16 ................................................................................................................. 37
• Added "1: Enabled" and "0: Disabled" to Description for Register D Bit 5 in Table 16........................................................ 38
• Added "(phase detector charge pump enabled)" and "(frequency detector charge pump enabled)" in Table 16 for
Address 1B Bits 1 and 0, respectively.................................................................................................................................. 40
• Updated contents of address 1F in Table 16 ...................................................................................................................... 41
• Added descriptions for Address 30 in Table 16 .................................................................................................................. 43
• Changed "0" to "1" for Address 31 Bit 5 in Table 16............................................................................................................ 44
Changes from Revision E (May 2013) to Revision F
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
2 Submit Documentation Feedback
Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: DS125DF410


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity DS125DF410 SNLS398H – JANUARY 2012 – REVISED FEBRUARY 2018 DS125DF 410 Low Power Multi-Rate Quad Channel R etimer 1 Features •1 Each Channel In dependently Locks to Data Rates from 9. 8 to 12.5 Gbps and Submultiples • Fas t Lock Operation Based on Protocol-Sele ct Mode • Low Latency (~300ps) • Ad aptive Equalization up to 34-dB Boost a t 5 GHz • Adjustable Transmit VOD: 60 0 to 1300 mVp-p • Adjustable Transmit De-emphasis to –15 dB • Typical Po wer Dissipation (EQ+DFE+CDR+DE): 180 mW /Channel • Programmable Output Polari ty Inversion • Input Signal Detection , CDR Lock Detection/Indicator • On-C hip Eye Monitor (EOM), PRBS Generator Single 2.5-V ± 5% Power Supply • SMBus/EEPROM Configuration Modes • Op erating Temperature Range of –40 to 8 5°C • WQFN 48-Pin 7-mm x 7-mm Packag e • Easy Pin Compatible Upgrade Betwe en Repeater and Retimers – DS100RT410 (EQ+CDR+DE): 10.3125 Gbps – DS100DF410 (EQ+DFE+CDR+DE): 10.3125 G.
Keywords DS125DF410, datasheet, pdf, etcTI, Low, Power, Multi-Rate, Quad, Channel, Retimer, S125DF410, 125DF410, 25DF410, DS125DF41, DS125DF4, DS125DF, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)