DRV8305-Q1 Driver Datasheet

DRV8305-Q1 Datasheet, PDF, Equivalent


Part Number

DRV8305-Q1

Description

Three-Phase Automotive Smart Gate Driver

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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DRV8305-Q1
SLVSD12D – MAY 2015 – REVISED JULY 2019
DRV8305-Q1 Three-Phase Automotive Smart Gate Driver With Three Integrated Current
Shunt Amplifiers and Voltage Regulator
1 Features
1 AEC-Q100 qualified for automotive applications
• Ambient operating temperature ranges:
– Temperature grade 0 (E): –40°C to +150°C
– Temperature grade 1 (Q): –40°C to +125°C
• 4.4-V to 45-V operating voltage
• 1.25-A and 1-A Peak gate drive currents
• Smart gate drive architecture (IDRIVE & TDRIVE)
• Programmable high- and low-side slew-rate
control
• Charge-pump gate driver for 100% duty cycle
• Three integrated current-shunt amplifiers
• Integrated 50-mA LDO (3.3-V and 5-V option)
• 3-PWM or 6-PWM input control up to 200 kHz
• Single PWM-mode commutation capability
• Serial Peripheral Interface (SPI) for device
settings and fault reporting
• Thermally-enhanced 48-Pin HTQFP
• Protection features:
– Fault diagnostics and MCU watchdog
– Programmable dead-time control
– MOSFET shoot-through prevention
– MOSFET VDS overcurrent monitors
– Gate-driver fault detection
– Reverse battery-protection support
– Limp home-mode support
– Overtemperature warning and shutdown
2 Applications
• Three-phase BLDC and PMSM motors
• Automotive fuel and water pumps
• Automotive fans and blowers
3 Description
The DRV8305-Q1 device is a gate driver IC for three-
phase motor-drive applications. The device provides
three high-accuracy half-bridge drivers, each capable
of driving a high-side and low-side N-channel
MOSFET. A charge pump driver supports 100% duty
cycle and low-voltage operation for cold crank
situations. The device can tolerate load dump
voltages up to 45-V.
The DRV8305-Q1 device includes three bidirectional
current-shunt amplifiers for accurate low-side current
measurements that support variable gain settings and
an adjustable offset reference.
The DRV8305-Q1 device has an integrated voltage
regulator to support an MCU or other system power
requirements. The voltage regulator can be interfaced
directly with a LIN physical interface to allow low-
system standby and sleep currents.
The gate driver uses automatic handshaking when
switching to prevent current shoot through. The VDS
of both the high-side and low-side MOSFETs is
accurately sensed to protect the external MOSFETs
from overcurrent conditions. The SPI provides
detailed fault reporting, diagnostics, and device
configurations such as gain options for the current
shunt amplifier, individual MOSFET overcurrent
detection, and gate-drive slew-rate control.
Device Options:
• DRV8305NQ: Grade 1 with voltage reference
• DRV83053Q: Grade 1 with 3.3-V, 50-mA LDO
• DRV83055Q: Grade 1 with 5-V, 50-mA LDO
• DRV8305NE: Grade 0 with voltage reference
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DRV8305-Q1
HTQFP (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
4.4 to 45 V
EN_GATE
PWM
SPI
Shunt Amps
nFAULT
50-mA LDO
DRV8305-Q1
Automotive
3-Phase
Brushless
Gate Driver
LDO
Shunt Amps
Protection
Gate Drive
Sense
M
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRV8305-Q1
DRV8305-Q1
SLVSD12D – MAY 2015 – REVISED JULY 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information .................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 SPI Timing Requirements (Slave Mode Only) ........ 14
6.7 Typical Characteristics ............................................ 15
7 Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 33
7.5 Programming........................................................... 35
7.6 Register Maps ......................................................... 37
8 Application and Implementation ........................ 45
8.1 Application Information............................................ 45
8.2 Typical Application .................................................. 46
9 Power Supply Recommendations...................... 50
9.1 Power Supply Consideration in Generator Mode ... 50
9.2 Bulk Capacitance ................................................... 50
10 Layout................................................................... 52
10.1 Layout Guidelines ................................................. 52
10.2 Layout Example .................................................... 52
11 Device and Documentation Support ................. 53
11.1 Documentation Support ........................................ 53
11.2 Receiving Notification of Documentation Updates 53
11.3 Community Resources.......................................... 53
11.4 Trademarks ........................................................... 53
11.5 Electrostatic Discharge Caution ............................ 53
11.6 Glossary ................................................................ 53
12 Mechanical, Packaging, and Orderable
Information ........................................................... 53
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2017) to Revision D
Page
• Added content to the VREG pin description........................................................................................................................... 5
• Added ESD classification levels to the ESD Ratings table .................................................................................................... 6
• Added the VREG Reference Voltage Input (DRV8305N) section ....................................................................................... 48
• Added the Power Supply Consideration in Generator Mode section ................................................................................... 50
Changes from Revision B (May 2016) to Revision C
Page
• Added transient specification for GHx, SLx, SPx, and SNx ................................................................................................... 6
• Changed SPx and SNx rating from -2 V to -3 V..................................................................................................................... 6
• Changed the test condition for the VAVDD_UVLO, VVCPH_UVFL, VVCPH_UVLO2, and VVCP_LSD_UVLO2 parameters in the
Electrical Characteristics table ............................................................................................................................................ 11
• Changed the maximum VAVDD_UVLO and VPVDD_UVLO2 parameters in the Electrical Characteristics table ............................. 11
• Moved the External Components table from the Pin Configuration and Functions section to the Feature Description
section .................................................................................................................................................................................. 18
• Added the description for latch fault reset methods to the Undervoltage Warning (UVFL), Undervoltage Lockout
(UVLO), and Overvoltage (OV) Protection section............................................................................................................... 32
• Changed the description of FLIP_OTSD register bit in the IC Operation Register Description ........................................... 42
• Added the Receiving Notification of Documentation Updates section ................................................................................. 53
Changes from Revision A (March 2016) to Revision B
Page
• Changed from PRODUCT PREVIEW to Production Data and released full data sheet........................................................ 1
2 Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
Product Folder Links: DRV8305-Q1


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity Reference Design DRV8305-Q1 SL VSD12D – MAY 2015 – REVISED JULY 20 19 DRV8305-Q1 Three-Phase Automotive Sm art Gate Driver With Three Integrated C urrent Shunt Amplifiers and Voltage Reg ulator 1 Features •1 AEC-Q100 qualif ied for automotive applications • Amb ient operating temperature ranges: – Temperature grade 0 (E): –40°C to +1 50°C – Temperature grade 1 (Q): –4 0°C to +125°C • 4.4-V to 45-V opera ting voltage • 1.25-A and 1-A Peak ga te drive currents • Smart gate drive architecture (IDRIVE & TDRIVE) • Prog rammable high- and low-side slew-rate c ontrol • Charge-pump gate driver for 100% duty cycle • Three integrated cu rrent-shunt amplifiers • Integrated 5 0-mA LDO (3.3-V and 5-V option) • 3-P WM or 6-PWM input control up to 200 kHz • Single PWM-mode commutation capabi lity • Serial Peripheral Interface (S PI) for device settings and fault reporting • Thermally-enhanced 48-Pin HTQFP • Protection features: – .
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