LM4312 Serializer Datasheet

LM4312 Datasheet, PDF, Equivalent


Part Number

LM4312

Description

RGB Display Differential Interface Serializer

Manufacture

National Semiconductor

Total Page 20 Pages
Datasheet
Download LM4312 Datasheet


LM4312
May 12, 2008
LM4312
Mobile Pixel Link Two (MPL-2), RGB Display Differential
Interface Serializer with Optional Dithering and Look Up
Table
General Description
The LM4312 is a MPL-2 Serializer (SER) that accepts a 24-
or 18-RGB interface and serializes this wide bus to 3 differ-
ential signals. The optional Dithering feature can reduce 24-
bit RGB to 18-bit RGB. The optional Look Up Table (Three X
256 X 8 bit RAM) is provided for independent color correction.
18-bit Bufferless displays from QVGA (320 x 240) up to >VGA
(640 x 480) pixels are supported.
The interconnect is reduced from 28 LVCMOS signals
(RGB888+V+H+DE+PCLK) to only 3 active differential sig-
nals (DD0P/M, DCP/M, DD1P/M) with the LM4312 Serializer
and companion LM4310 Deserializer easing flex interconnect
design, size constraints and cost.
The LM4312 SER resides by the application, graphics or
baseband processor and translates the wide parallel video
bus from LVCMOS levels to serial MPL-2 levels for transmis-
sion over a flex cable and PCB traces to the DES located in
the display module.
When in Power_Down, the SER is put to sleep and draws less
than 10μA. The SER can be powered down by stopping the
PCLK or by asserting its PD* input pin.
The LM4312 implements the physical layer of the MPL-2 In-
terface and features robust common-mode noise rejection.
Features
RGB Display Interface to >640 x 480 (VGA) Resolution
24 or 18-bit RGB Transport
24–to–18-bit RGB Dithering option
Look Up Table option for independent color correction
option
Robust MPL-2 Differential SLVS Interface
SPI Interface for configuration / control and LUT options
Low Power Consumption & SLEEP state
Auto Power Down on STOP PCLK
Automatically generates frame sequence bits for resync
upon data or clock error
Odd Parity Generation
System Benefits
Dithered Data Reduction
Independent RGB Color Correction
24-bit Color Input
Small Robust Interface
Low Power & Low EMI
Typical Application Diagram - Bridge Chips - 24-bit to 18-bit RGB
Ordering Information
NSID
LM4312
Package Type
48L LLP, 6mm x 6mm x 0.4mm, 0.4mm pitch
© 2008 National Semiconductor Corporation 300116
30011601
Package ID
TBD
www.national.com

LM4312
Pin Descriptions
Pin Name
No.
of Pins
I/O, Type
Description
RGB Serializer
MPL-2 SERIAL BUS PINS
DD0P, DD0M,
DD1P, DD1M
4 O, MPL-2 MPL-2 Differential Data Line Driver True (Plus) and Compliment (Minus) Outputs
Channel 0 and 1
DCP, DCM
2 O, MPL-2 MPL-2 Differential Clock Line Driver True (Plus) and Compliment (Minus) Outputs
SPI INTERFACE and CONFIGURATION PINS
SPI_CSX
1 I, SPI_Chip Select Input
LVCMOS SPI port is enabled when: SPI_CSX is Low, PD* is High.
SPI_SCL
1 I, SPI_Clock Input
LVCMOS
SPI_DI
1 I, SPI Data Input
LVCMOS
SPI_DO
1 O, SPI Data Output
LVCMOS
PD* 1 I, Power Down Mode Input
LVCMOS PD* = Low, SER is in SLEEP Mode,
SPI Registers are RESET, LUT Data is retained.
PD* = High and PCLK = Stopped, SER is in SLEEP Mode,
SPI Register settings are retained and LUT data is retained.
PD* = High, Device is enabled.
RES1
1 I, Tie High
LVCMOS
TM 1 I Tie Low
LVCMOS H = Test Mode (Reserved)
VIDEO INTERFACE PINS
PCLK
1 I, Pixel Clock Input
LVCMOS Video Signals are latched on the RISING edge.
R[7:0]
G[7:0]
B[7:0]
24 I, RGB Data Bus Inputs – Bit 7 is the MSB.
LVCMOS 24-bit Mode - use RGB[7:0]
18-bit Mode - use RGB[7:2], tie off RGB[1:0] to GND, do not float.
VS 1 I, Vertical Sync. Input
LVCMOS This signal is used as a frame start for the Dither block and is required when
Dither option is selected.
The VS signal is serialized unmodified.
HS 1 I, Horizontal Sync. Input
LVCMOS
DE 1 I, Data Enable Input
LVCMOS
POWER/GROUND PINS
VDD 7 Power Supply Power Supply Pins. All VDD pins must be connect to power supply.
1.6V to 2.0V
VSS 1 Ground Ground Pin
DAP pad must be connected to Ground.
Note:
I = Input, O = Output, IO = Input/Output. Do not float unused input pins.
www.national.com
2


Features LM4312 Mobile Pixel Link Two (MPL-2), RG B Display Differential Interface Serial izer with Optional Dithering and Look U p Table May 12, 2008 LM4312 Mobile Pi xel Link Two (MPL-2), RGB Display Diffe rential Interface Serializer with Optio nal Dithering and Look Up Table Genera l Description The LM4312 is a MPL-2 Ser ializer (SER) that accepts a 24or 18-RG B interface and serializes this wide bu s to 3 differential signals. The option al Dithering feature can reduce 24bit R GB to 18-bit RGB. The optional Look Up Table (Three X 256 X 8 bit RAM) is prov ided for independent color correction. 18-bit Bufferless displays from QVGA (3 20 x 240) up to >VGA (640 x 480) pixels are supported. The interconnect is red uced from 28 LVCMOS signals (RGB888+V+H +DE+PCLK) to only 3 active differential signals (DD0P/M, DCP/M, DD1P/M) with t he LM4312 Serializer and companion LM43 10 Deserializer easing flex interconnec t design, size constraints and cost. Th e LM4312 SER resides by the application, graphics or baseband p.
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