SN74LVC138A-Q1 Demultiplexers Datasheet

SN74LVC138A-Q1 Datasheet, PDF, Equivalent


Part Number

SN74LVC138A-Q1

Description

3-Line to 8-Line Decoders Demultiplexers

Manufacture

etcTI

Total Page 15 Pages
Datasheet
Download SN74LVC138A-Q1 Datasheet


SN74LVC138A-Q1
www.ti.com
SN74LVC138A-Q1
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS708B – SEPTEMBER 2003 – REVISED FEBRUARY 2008
FEATURES
1
Qualified for Automotive Applications
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.8 ns at 3.3 V
Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 2 V
at VCC = 3.3 V, TA = 25°C
D OR PW PACKAGE
(TOP VIEW)
A
B
C
G2A
G2B
G1
Y7
GND
1
2
3
4
5
6
7
8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
DESCRIPTION/ORDERING INFORMATION
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very short
propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system
decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder
and the enable time of the memory usually are less than the typical access time of the memory. This means that
the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only
one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
TA
–40°C to 125°C
SOIC – D
TSSOP – PW
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
Reel of 2500
SN74LVC138AQDRQ1
Reel of 2000
SN74LVC138AQPWRQ1
TOP-SIDE MARKING
L138AQ1
L138AQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2008, Texas Instruments Incorporated

SN74LVC138A-Q1
SN74LVC138A-Q1
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS708B – SEPTEMBER 2003 – REVISED FEBRUARY 2008
www.ti.com
FUNCTION TABLE
ENABLE INPUTS SELECT INPUTS
OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XHXXXXHHHHHHHH
XXHXXXHHHHHHHH
L XXXXXHHHHHHHH
HL L L L L LHHHHHHH
HL L L LHHL HHHHHH
HL L L HLHHLHHHHH
HL L L HHHHHLHHHH
HL LHL LHHHHL HHH
HL LHLHHHHHHLHH
HL LHHLHHHHHHLH
HL LHHHHHHHHHHL
LOGIC DIAGRAM (POSITIVE LOGIC)
1
A
Select
Inputs
2
B
3
C
6
G1
Enable
Inputs
4
G2A
5
G2B
15 Y0
14 Y1
13
Y2
12 Y3
11 Y4
Data
Outputs
10 Y5
9 Y6
7
Y7
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Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC138A-Q1


Features www.ti.com SN74LVC138A-Q1 3-LINE TO 8-L INE DECODER/DEMULTIPLEXER SCAS708B – SEPTEMBER 2003 – REVISED FEBRUARY 200 8 FEATURES 1 • Qualified for Automot ive Applications • ESD Protection Exc eeds 2000 V Per MIL-STD-883, Method 301 5; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) • Operates From 2 V to 3.6 V • Inputs Accept Voltages to 5.5 V • Max tpd of 5.8 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C D OR PW PACKAGE (TOP VIEW) A B C G2A G2B G1 Y 7 GND 1 2 3 4 5 6 7 8 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 DESCR IPTION/ORDERING INFORMATION The SN74LVC 138A 3-line to 8-line decoder/demultipl exer is designed for 2.7-V to 3.6-V VCC operation. The device is designed for high-performance memory-decoding or dat a-routing applications requiring very s hort propagation delay times. In high-p erformance memory systems, this decoder minimizes the effects of system decoding. W.
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