CD54HC4059 Logic Datasheet 

Part Number  CD54HC4059 
Description  HighSpeed CMOS Logic 
Manufacture  etcTI 
Total Page  12 Pages 
Datasheet 
CD54HC4059, CD74HC4059
Data sheet acquired from Harris Semiconductor
SCHS206B
February 1998  Revised May 2003
HighSpeed CMOS Logic
CMOS Programmable DividebyN Counter
[ /Title
(CD74
HC4059
)
/Sub
ject
(High
Speed
CMOS
Logic
CMOS
Pro
Features
Description
• Synchronous Programmable ÷N Counter N = 3 to 9999
or 15999
• Presettable DownCounter
• Fully Static Operation
• ModeSelect Control of Initial Decade Counting
Function (÷10, 8, 5, 4, 2)
• Master Preset Initialization
• Latchable ÷N Output
• Fanout (Over Temperature Range)
 Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
 Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . 55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Signiﬁcant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
 2V to 6V Operation
 High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
The ’HC4059 are highspeed silicongate devices that are
pincompatible with the CD4059A devices of the CD4000B
series. These devices are dividebyN downcounters that
can be programmed to divide an input frequency by any
number “N” from 3 to 15,999. The output signal is a pulse
one clock cycle wide occurring at a rate equal to the input
frequency divide by N. The downcounter is preset by means
of 16 jam inputs.
The three ModeSelect Inputs Ka, Kb and Kc determine the
modulus (“divideby” number) of the first and last counting
sections in accordance with the truth table. Every time the first
(fastest) counting section goes through one cycle, it reduces by
1 the number that has been preset (jammed) into the three
decades of the intermediate counting section an the last
counting section, which consists of flipflops that are not
needed for opening the first counting section. For example, in
the ÷2 mode, only one flipflop is needed in the first counting
section. Therefore the last counting section has three flipflops
that can be preset to a maximum count of seven with a place
value of thousands. If ÷10 is desired for the first section, Ka is
set “high”, Kb “high” and Kc “low”. Jam inputs J1, J2, J3, and J4
are used to preset the first counting section and there is no last
counting section. The intermediate counting section consists of
three cascaded BCD decade (÷10) counters presettable by
means of Jam Inputs J5 through J16.
Applications
• Communications Digital Frequency Synthesizers;
VHF, UHF, FM, AM, etc.
• Fixed or Programmable Frequency Division
• “Time Out” Timer for ConsumerApplication Industrial
Controls
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC4059F3A
55 to 125
24 Ld CERDIP
CD74HC4059E
55 to 125
24 Ld PDIP
CD74HC4059M96
55 to 125
24 Ld SOIC
NOTE: When ordering, use the entire part number. The sufﬁx 96
denotes tape and reel.
The ModeSelect Inputs permit frequencysynthesizer
channel separations of 10, 12.5, 20, 25 or 50 parts. These
inputs set the maximum value of N at 9999 (when the ﬁrst
counting section divides by 5 or 10) or 15,999 (when the ﬁrst
counting section divides by 8, 4, or 2).
The three decades of the intermediate counter can be preset
to a binary 15 instead of a binary 9, while their place values
are still 1, 10, and 100, multiplied by the number of the ÷N
mode. For example, in the ÷8 mode, the number from which
counting down begins can be preset to:
3rd Decade
1500
2nd Decade
150
1st Decade
15
Last Counting Section 1000
The total of these numbers (2665) times 8 equals 12,320.
The ﬁrst counting section can be preset to 7. Therefore,
21,327 is the maximum possible count in the ÷8 mode.
The highest count of the various modes is shown in the
Extended Counter Range column. Control inputs Kb and Kc
can be used to initiate and lock the counter in the “master
preset” state. In this condition the flipflops in the counter are
preset in accordance with the jam inputs and the counter
remains in that state as long as Kb and Kc both remain low. The
counter begins to count down from the preset state when a
counting mode other than the master preset mode is selected.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1

CD54HC4059, CD74HC4059
The counter should always be put in the master preset mode
before the ÷5 mode is selected. Whenever the master preset
mode is used, control signals Kb = “low” and Kc = “low” must
be applied for at least 3 full clock pulses.
Pinout
After Preset Mode inputs have been changed to one of the ÷
modes, the next positivegoing clock transition changes an
internal ﬂipﬂop so that the countdown can begin at the
second positivegoing clock transition. Thus, after an MP
(Master Preset) mode, there is always one extra count
before the output goes high. Figure 1 illustrates a total count
of 3 (÷8 mode). If the Master Preset mode is started two
clock cycles or less before an output pulse, the output pulse
will appear at the time due. If the Master Preset Mode is not
used, the counter jumps back to the “Jam” count when the
output pulse appears.
A “high” on the Latch Enable input will cause the counter
output to remain high once an output pulse occurs, and to
remain in the high state until the latch input returns to “low”.
If the Latch Enable is “low”, the output pulse will remain high
for only one cycle of the clockinput signal.
CD54HC4059
(CERDIP)
CD74HC4059
(PDIP, SOIC)
TOP VIEW
CP 1
LE 2
J1 3
J2 4
J3 5
J4 6
J16 7
J15 8
J14 9
J13 10
Kc 11
GND 12
24 VCC
23 Q
22 J5
21 J6
20 J7
19 J8
18 J9
17 J10
16 J11
15 J12
14 Ka
13 Kb
Functional Diagram
J1  J16
CP
Ka
Kb
Q=
fNIN
Kc
LE
TRUTH TABLE
COUNTER RANGE
MODE SELECT INPUT
FIRST COUNTING SECTION
LAST COUNTING SECTION
DESIGN EXTENDED
CAN BE (NOTE 1)
CAN BE (NOTE 1)
PRESET
JAM
PRESET
JAM
MODE TO A MAX INPUTS
MODE TO A MAX INPUTS
Ka Kb Kc DIVIDESBY OF:
USED: DIVIDESBY OF:
USED:
MAX
HHH
2
1 J1
8
7 J2, J3, J4 15,999
MAX
17,331
L HH
4
3 J1, J2
4
3
J3, J4
15,999
18,663
HLH
5
(Note 2)
4 J1, J2, J3
2
1
J4
9,999
13,329
L LH
8
7 J1, J2, J3
2
1
J4
15,999
21,327
HH L
10
9 J1, J2, J3, J4
1
0

9,999
16,659
XLL
Master Preset
Master Preset

X = Don’t care
NOTES:
1. J1 = Least Signiﬁcant Bit. J4 = Most Signiﬁcant Bit.
2. Operation in the 5mode (1st counting section) requires going through the Master Preset mode prior to going into the 5mode. At power
turnon, Kc must be “low” for a period of 3 input clock pulses after VCC reaches a minimum of 3V.
2

Features  CD54HC4059, CD74HC4059 Data sheet acqui red from Harris Semiconductor SCHS206B February 1998  Revised May 2003 High Speed CMOS Logic CMOS Programmable Divi debyN Counter [ /Title (CD74 HC4059 ) /Subject (HighSpeed CMOS Logic CMOS P ro Features Description • Synchro nous Programmable ÷N Counter N = 3 to 9999 or 15999 • Presettable DownCoun ter • Fully Static Operation • Mode Select Control of Initial Decade Count ing Function (÷10, 8, 5, 4, 2) • Mas ter Preset Initialization • Latchable ÷N Output • Fanout (Over Temperatur e Range)  Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads  Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Te mperature Range . . . 55oC to 125oC Balanced Propagation Delay and Transi tion Times • Signiﬁcant Power Reduc tion Compared to LSTTL Logic ICs • HC Types  2V to 6V Operation  High Nois e Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V The ’HC4059 are highspeed silicongate devices that are pincompatible with. 
Keywords  CD54HC4059, datasheet, pdf, etcTI, HighSpeed, CMOS, Logic, D54HC4059, 54HC4059, 4HC4059, CD54HC405, CD54HC40, CD54HC4, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute 

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact) 