CD54HC4059

CD54HC4059, CD74HC4059 Data sheet acquired from Harris Semiconductor SCHS206B February 1998 - Revised May 2003 High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter [ /Title (CD74 HC4059 ) /Subject (HighSpeed CMOS Logic CMOS Pro- Features Description Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 Presettable Down-Counter Fully Static Operation Mode-Select Control of Initial Decade Counting Function (÷10, 8, 5, 4, 2) Master Preset Initialization Latchable ÷N Output Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V The ’HC4059 are high-speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series. These devices are divide-by-N down-counters that can be programmed to divide an input frequency by any number “N” from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The down-counter is preset by means of 16 jam inputs. The three Mode-Select Inputs Ka, Kb and Kc determine the modulus (“divide-by” number) of the first and last counting sections in accordance with the truth tab...