STM32MP151A MPU Datasheet

STM32MP151A Datasheet, PDF, Equivalent


Part Number

STM32MP151A

Description

Arm Cortex-A7 650MHz + Cortex-M4 MPU

Manufacture

STMicroelectronics

Total Page 30 Pages
Datasheet
Download STM32MP151A Datasheet


STM32MP151A
STM32MP151A
Arm® Cortex®-A7 650 MHz + Cortex®-M4 MPU,
TFT, 35 comm. interfaces, 25 timers, adv. analog
Datasheet - production data
Features
Core
32-bit Arm® Cortex®-A7
– L1 32-Kbyte I / 32-Kbyte D
– 256-Kbyte unified level 2 cache
– Arm® NEON™ and Arm® TrustZone®
32-bit Arm® Cortex®-M4 with FPU/MPU
– Up to 209 MHz (Up to 703 CoreMark®)
Memories
External DDR memory up to 1 Gbyte
– up to LPDDR2/LPDDR3-1066 16/32-bit
– up to DDR3/DDR3L-1066 16/32-bit
708 Kbytes of internal SRAM: 256 Kbytes of
AXI SYSRAM + 384 Kbytes of AHB SRAM +
64 Kbytes of AHB SRAM in Backup domain
and 4 Kbytes of SRAM in Backup domain
Dual mode Quad-SPI memory interface
Flexible external memory controller with up to
16-bit data bus: parallel interface to connect
external ICs and SLC NAND memories with up
to 8-bit ECC
Security/safety
TrustZone® peripherals, active tamper
Cortex®-M4 resources isolation
Reset and power management
1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
POR, PDR, PVD and BOR
On-chip LDOs (RETRAM, BKPSRAM, USB
1.8 V, 1.1 V)
Backup regulator (~0.9 V)
Internal temperature sensors
Low-power modes: Sleep, Stop and Standby
LPDDR2/3 retention in Standby mode
LFBGA
TFBGA
LFBGA448 (18 × 18mm)
LFBGA354 (16 × 16mm)
Pitch 0.8mm
TFBGA361 (12 × 12 mm)
TFBGA257 (10 × 10 mm)
min Pitch 0.5mm
Controls for PMIC companion chip
Low-power consumption
Total current consumption down to 2 µA
(Standby mode, no RTC, no LSE, no BKPSRAM, no
RETRAM)
Clock management
Internal oscillators: 64 MHz HSI oscillator,
4 MHz CSI oscillator, 32 kHz LSI oscillator
External oscillators: 8-48 MHz HSE oscillator,
32.768 kHz LSE oscillator
5 × PLLs with fractional mode
General-purpose input/outputs
Up to 176 I/O ports with interrupt capability
– Up to 8 secure I/Os
– Up to 6 Wakeup, 3 tampers, 1 active
tamper
Interconnect matrix
2 bus matrices
– 64-bit Arm® AMBA® AXI interconnect, up to
266 MHz
– 32-bit Arm® AMBA® AHB interconnect, up
to 209 MHz
3 DMA controllers to unload the CPU
48 physical channels in total
1 × high-speed general-purpose master direct
memory access controller (MDMA)
August 2019
This is information on a product in full production.
DS12500 Rev 2
1/254
www.st.com

STM32MP151A
STM32MP151A
2 × dual-port DMAs with FIFO and request
router capabilities for optimal peripheral
management
Up to 35 communication peripherals
6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
4 × UART + 4 × USART (12.5 Mbit/s, ISO7816
interface, LIN, IrDA, SPI slave)
6 × SPI (50 Mbit/s, including 3 with full duplex
I2S audio class accuracy via internal audio PLL
or external clock)
4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
SPDIF Rx with 4 inputs
HDMI-CEC interface
MDIO Slave interface
3 × SDMMC up to 8-bit (SD / e•MMC/ SDIO)
2 × USB 2.0 high-speed Host
+ 1 × USB 2.0 full-speed OTG simultaneously
– or 1 × USB 2.0 high-speed Host
+ 1 × USB 2.0 high-speed OTG
simultaneously
10/100M or Gigabit Ethernet GMAC
– IEEE 1588v2 hardware,
MII/RMII/GMII/RGMII
8- to 14-bit camera interface up to 140 Mbyte/s
6 analog peripherals
2 × ADCs with 16-bit max. resolution (12 bits
up to 4.5 Msps, 14 bits up to 4 Msps, 16 bits up
to 3.6 Msps)
1 × temperature sensor
2 × 12-bit D/A converters (1 MHz)
1 × digital filters for sigma delta modulator
(DFSDM) with 8 channels/6 filters
Internal or external ADC/DAC reference VREF+
Graphics
LCD-TFT controller, up to 24-bit // RGB888
– up to WXGA (1366 × 768) @60 fps
– Two layers with programmable colour LUT
Up to 25 timers and 3 watchdogs
2 × 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
2 × 16-bit advanced motor control timers
10 × 16-bit general-purpose timers (including 2
basic timers without PWM)
5 × 16-bit low-power timers
RTC with sub-second accuracy and hardware
calendar
4 Cortex®-A7 system timers (secure, non-
secure, virtual, hypervisor)
1 × SysTick M4 timer
3 × watchdogs (2 × independent and window)
Hardware acceleration
HASH (MD5, SHA-1, SHA224, SHA256),
HMAC
2 × true random number generator
(3 oscillators each)
2 × CRC calculation unit
Debug mode
Arm® CoreSight™ trace and debug: SWD and
JTAG interfaces
8-Kbyte embedded trace buffer
3072-bit fuses including 96-bit unique ID,
up to 1184-bit available for user
All packages are ECOPACK2 compliant
2/254
DS12500 Rev 2


Features STM32MP151A Arm® Cortex®-A7 650 MHz + Cortex®-M4 MPU, TFT, 35 comm. interfa ces, 25 timers, adv. analog Datasheet - production data Features Core • 32- bit Arm® Cortex®-A7 – L1 32-Kbyte I / 32-Kbyte D – 256-Kbyte unified lev el 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M 4 with FPU/MPU – Up to 209 MHz (Up to 703 CoreMark®) Memories • External DDR memory up to 1 Gbyte – up to LPDD R2/LPDDR3-1066 16/32-bit – up to DDR3 /DDR3L-1066 16/32-bit • 708 Kbytes of internal SRAM: 256 Kbytes of AXI SYSRA M + 384 Kbytes of AHB SRAM + 64 Kbytes of AHB SRAM in Backup domain and 4 Kbyt es of SRAM in Backup domain • Dual mo de Quad-SPI memory interface • Flexib le external memory controller with up t o 16-bit data bus: parallel interface t o connect external ICs and SLC NAND mem ories with up to 8-bit ECC Security/saf ety • TrustZone® peripherals, active tamper • Cortex®-M4 resources isola tion Reset and power management • 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) • POR, PDR, PVD and BOR .
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