SN54HC139 DECODERS/DEMULTIPLEXERS Datasheet

SN54HC139 Datasheet, PDF, Equivalent


Part Number

SN54HC139

Description

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

Manufacture

etcTI

Total Page 22 Pages
Datasheet
Download SN54HC139 Datasheet


SN54HC139
SN54HC139, SN74HC139
DUAL 2ĆLINE TO 4ĆLINE DECODERS/DEMULTIPLEXERS
D Targeted Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 10 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
description/ordering information
The ’HC139 devices are designed for
high-performance memory-decoding or
data-routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can minimize
the effects of system decoding. When employed
with high-speed memories utilizing a fast enable
circuit, the delay time of these decoders and the
enable time of the memory usually are less than
the typical access time of the memory. This means
that the effective system delay introduced by the
decoders is negligible.
SCLS108D − DECEMBER 1982 − REVISED SEPTEMBER 2003
SN54HC139 . . . J OR W PACKAGE
SN74HC139 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
GND
1
2
3
4
5
6
7
8
16 VCC
15 2G
14 2A
13 2B
12 2Y0
11 2Y1
10 2Y2
9 2Y3
SN54HC139 . . . FK PACKAGE
(TOP VIEW)
1B
3 2 1 20 19
4 18
2A
1Y0 5
17 2B
NC 6
16 NC
1Y1 7
15 2Y0
1Y2 8
14 2Y1
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC139N
SN74HC139N
Tube of 40
SN74HC139D
SOIC − D
Reel of 2500
Reel of 250
SN74HC139DR
SN74HC139DT
HC139
−40°C to 85°C
SOP − NS
SSOP − DB
Reel of 2000
Reel of 2000
SN74HC139NSR
SN74HC139DBR
HC139
HC139
Tube of 90
SN74HC139PW
TSSOP − PW
Reel of 2000
Reel of 250
SN74HC139PWR
SN74HC139PWT
HC139
CDIP − J
Tube of 25
SNJ54HC139J
SNJ54HC139J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC139W
SNJ54HC139W
LCCC − FK
Tube of 55
SNJ54HC139FK
SNJ54HC139FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

SN54HC139
SN54HC139, SN74HC139
DUAL 2ĆLINE TO 4ĆLINE DECODERS/DEMULTIPLEXERS
SCLS108D − DECEMBER 1982 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The ’HC139 devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable
(G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully
buffered inputs, each of which represents only one normalized load to its driving circuit.
FUNCTION TABLE
INPUTS
SELECT
G
BA
HXX
OUTPUTS
Y0 Y1 Y2
HHH
L L L LHH
L LHHLH
L H L HH L
L HHHHH
Y3
H
H
H
H
L
logic diagram (positive logic)
1
1G
4
1Y0
5
1Y1
2
1A
3
1B
15
2G
6
1Y2
7
1Y3
12
2Y0
11
2Y1
14
2A
13
2B
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
10
2Y2
9
2Y3
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features SN54HC139, SN74HC139 DUAL 2ĆLINE TO 4Ć LINE DECODERS/DEMULTIPLEXERS D Targete d Specifically for High-Speed Memory De coders and Data-Transmission Systems D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA M ax ICC D Typical tpd = 10 ns D ±4-mA O utput Drive at 5 V D Low Input Current of 1 µA Max D Incorporate Two Enable I nputs to Simplify Cascading and/or Data Reception description/ordering informa tion The ’HC139 devices are designed for high-performance memory-decoding or data-routing applications requiring ve ry short propagation delay times. In hi gh-performance memory systems, these de coders can minimize the effects of syst em decoding. When employed with high-sp eed memories utilizing a fast enable ci rcuit, the delay time of these decoders and the enable time of the memory usua lly are less than the typical access ti me of the memory. This means that the e ffective system delay introduced by the decoders is negligible. SCLS1.
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