ADIN1300 PHY Datasheet

ADIN1300 Datasheet, PDF, Equivalent


Part Number

ADIN1300

Description

10/100/1000 Gigabit Ethernet PHY

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download ADIN1300 Datasheet


ADIN1300
Preliminary Technical Data
Robust, Industrial, Low Latency
10/100/1000 Gigabit Ethernet PHY
ADIN1300
FEATURES
10BASE-Te/100BASE-TX/1000BASE-T IEEE® 802.3TM compliant
MII, RMII and RGMII MAC interfaces
1000BASE-T RGMII latency TX <68 ns, RX < 226 ns
100BASE-TX MII latency TX<52ns, RX < 248 ns
EMC Test Standards:
IEC 61000-4-5 surge (±3 kV)
IEC 61000-4-4 electrical fast transient (EFT) (±4 kV)
IEC 61000-4-2 ESD (±6 kV contact discharge)
IEC 61000-4-6 conducted immunity (10 V)
EN55022 radiated emissions (CLASS A)
EN55022 conducted emissions (CLASS B)
Unmanaged configuration using multi-level pin strapping
Energy Efficient Ethernet (EEE) in accordance with
IEEE 802.3az
Start of Frame Detection for IEEE 1588 Time Stamp Support
Enhanced Link Detection
Configurable LED
Crystal Oscillator/25MHz clock input (50 MHz for RMII)
25 MHz/125MHz Synchronous clock output
Small Package and Wide Temperature Range
40-lead (6 mm x 6 mm) LFCSP
Specified for -40°C to +105°C ambient operation
Low Power Consumption
332mW -1000BASE-T
140mW -100BASE-TX
3.3 V/2.5 V/1.8 V MAC interface VDDIO supply
Integrated power supply monitoring and POR
APPLICATIONS
Industrial automation
Process control
Factory automation
Robotics/Motion Control
Building automation
Test and Measurement
Industrial IoT
GENERAL DESCRIPTION
The ADIN1300 is a low power single port Gigabit Ethernet
transceiver with industry leading latency specifications
primarily designed for industrial Ethernet applications.
This design integrates an Energy Efficient Ethernet PHY core
plus all the associated common analog circuitry, input and
output clock buffering, the management interface and sub-
system registers as well as the MAC interface and control logic
to manage the reset and clock control and pin configuration.
The ADIN1300 is available in a 6 mm x 6 mm 40-ld package. If
a GMII MAC interface is required, the ADIN1301 can be used.
This is housed in a 9 mm x 9mm 64-ld package and also
provides two extra LED pins.
The device operates with a minimum of 2 power supplies – 0.9
V and 3.3 V, assuming the use of a 3.3 V MAC interface supply.
However, for maximum flexibility in system level design, the
separate VDDIO supply enables the MDIO and MAC interface
supply voltages to be configured independently of the other
circuitry on the ADIN1300 allowing operation at 1.8 V, 2.5 V or
3.3 V. At power-up, the ADIN1300 is held in hardware reset
until each of the supplies has crossed its minimum rising
threshold value and the power is considered good. Brown-out
protection is provided by monitoring the supplies to detect if
one or more of them drops below a minimum falling threshold
(see Table 16) and holding the part in hardware reset until the
power is good again.
The MII management interface (also referred to as MDIO
interface) provides a two-wire serial interface between a host
processor or MAC - also known as Management Station (STA) -
and the ADIN1300 allowing access to control and status
information in the PHY core management registers. The
interface is compatible with both IEEE 802.3 Std clause 22 and
clause 45 management frame structures.
Table 1. Related Products
Part No. Description
ADIN1301
Robust, Industrial, Low Latency Gigabit Ethernet
PHY with GMII Interface in 64-ld (9 mm x 9 mm)
LGA
ADIN1200 Robust, Industrial, Low Power 10/100 Ethernet
PHY in 32-ld (5 mm x 5 mm) LFCSP
Rev. PrF
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rightsofthird parties thatmayresult from itsuse. Specificationssubjectto change withoutnotice.
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Tel: 781.329.4700
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Fax: 781.461.3113
©2019 Analog Devices, Inc. All rights reserved.

ADIN1300
ADIN1300
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Theory of Operation ...................................................................... 17
Power Supply Domains.............................................................. 17
MAC Interface ............................................................................ 17
Management Interface ............................................................... 18
MDI Interface.............................................................................. 19
Reset Operation .......................................................................... 19
Powerdown Modes ..................................................................... 21
Status LED ................................................................................... 23
PHY Output Clocks ................................................................... 23
Preliminary Technical Data
Hardware Configuration Pins....................................................... 24
Hardware Configuration Pin Functions ................................. 24
On-Chip Diagnostics ..................................................................... 28
Loopback Modes ........................................................................ 28
Frame Generator And Checker................................................ 29
Cable Diagnostics....................................................................... 29
Enhanced Link Detection ......................................................... 29
Start of Packet Indication .......................................................... 30
Register Summary .......................................................................... 31
PHY Core Register Summary................................................... 31
PHY Core Register Details........................................................ 34
Sub-System Register Summary ................................................ 68
Sub-System Register Details ..................................................... 69
Applications Information .............................................................. 75
Supply Decoupling ..................................................................... 75
Layout Guidelines for LFCSP Package .................................... 75
Component Recommendations ............................................... 75
Outline Dimensions ....................................................................... 76
Rev. PrF | Page 2 of 76


Features Preliminary Technical Data Robust, Indu strial, Low Latency 10/100/1000 Gigabit Ethernet PHY ADIN1300 FEATURES 10BASE -Te/100BASE-TX/1000BASE-T IEEE® 802.3T M compliant MII, RMII and RGMII MAC int erfaces 1000BASE-T RGMII latency TX <68 ns, RX < 226 ns 100BASE-TX MII latency TX<52ns, RX < 248 ns EMC Test Standard s: IEC 61000-4-5 surge (±3 kV) IEC 610 00-4-4 electrical fast transient (EFT) (±4 kV) IEC 61000-4-2 ESD (±6 kV cont act discharge) IEC 61000-4-6 conducted immunity (10 V) EN55022 radiated emissi ons (CLASS A) EN55022 conducted emissio ns (CLASS B) Unmanaged configuration us ing multi-level pin strapping Energy Ef ficient Ethernet (EEE) in accordance wi th IEEE 802.3az Start of Frame Detectio n for IEEE 1588 Time Stamp Support Enha nced Link Detection Configurable LED Cr ystal Oscillator/25MHz clock input (50 MHz for RMII) 25 MHz/125MHz Synchronous clock output Small Package and Wide Te mperature Range 40-lead (6 mm x 6 mm) L FCSP Specified for -40°C to +105°C ambient operation Low Power Cons.
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