ADIN1200 PHY Datasheet

ADIN1200 Datasheet, PDF, Equivalent


Part Number

ADIN1200

Description

10 Mbps and 100 Mbps Ethernet PHY

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download ADIN1200 Datasheet


ADIN1200
Data Sheet
Robust, Industrial, Low Power,
10 Mbps and 100 Mbps Ethernet PHY
ADIN1200
FEATURES
10BASE-Te/100BASE-TX IEEE® 802.3TM compliant
MII, RMII and RGMII MAC interfaces
100BASE-TX RGMII latency transmit: <124 ns, receive <250 ns
100BASE-TX MII latency transmit: <52 ns, receive <248 ns
EMC test standards
IEC 61000-4-5 surge (±4 kV)
IEC 61000-4-4 electrical fast transient (EFT) (±4 kV)
IEC 61000-4-6 conducted immunity (10 V)
EN55032 radiated emissions (Class A)
EN55032 conducted emissions (Class A)
Unmanaged configuration using multilevel pin strapping
EEE in accordance with IEEE 802.3az
Start of packet detection for IEEE 1588 time stamp support
Enhanced link detection
Configurable LED
Crystal oscillator/clock input: 25 MHz
25 MHz/125 MHz synchronous clock output
Small package and wide temperature range
32-lead, 5 mm × 5 mm LFCSP
Specified for −40°C to +105°C and −40°C to +85°C ambient
operation
Low power consumption
139 mW for 100BASE-TX
3.3 V/2.5 V/1.8 V MAC interface VDDIO supply
Single-supply operation with 3.3 V VDDIO
Integrated power supply monitoring and POR
APPLICATIONS
Industrial automation
Process control
Factory automation
Robotics and motion control
Building automation
Test and measurement
Industrial internet of things (IoT)
GENERAL DESCRIPTION
The ADIN1200 is a low power, single-port, 10 Mbps and 100 Mbps
Ethernet transceiver with low latency specifications designed
for industrial Ethernet applications.
This design integrates an energy efficient Ethernet (EEE) physical
layer device (PHY) core with all associated common analog
circuitry, input and output clock buffering, management
interface and subsystem registers, and media access control
(MAC) interface and control logic to manage the reset, clock
control and pin configuration.
The ADIN1200 is available in a 5 mm × 5 mm, 32-lead lead
frame chip scale package (LFCSP) and can operate with a single
3.3 V supply, assuming the use of a 3.3 V MAC interface supply.
For maximum flexibility in system level design, a separate VDDIO
supply enables the management data input/output (MDIO) and
MAC interface supply voltages to be configured independently
of the other circuitry on the ADIN1200 allowing operation at
1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1200 is held in
hardware reset until each of the supplies has crossed its minimum
rising threshold value and the power is considered good. Brownout
protection is provided by monitoring the supplies to detect if
one or more of them drops below a minimum falling threshold
and holding the device in hardware reset until the power supplies
return and satisfy the power-on-reset (POR) circuit.
The MII management interface (also referred to as MDIO
interface) provides a 2-wire serial interface between a host
processor or MAC and the ADIN1200, allowing access to
control and status information in the PHY core management
registers. The interface is compatible with both IEEE® 802.3™
Standard Clause 22 and Clause 45 management frame
structures.
The ADIN1200 can support cable lengths up to 180 meters.
Note that throughout this data sheet, multifunction pins, such
as XTAL_I/CLK_IN/REF_CLK, are referred to either by the
entire pin name or by a single function of the pin, for example,
XTAL_I, when only that function is relevant.
Table 1. Related Products
Product No. Description
ADIN1300
Robust, industrial, low latency gigabit
Ethernet PHY in 40-lead (6 mm × 6 mm) LFCSP
Rev. 0
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ADIN1200
ADIN1200
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Revision History ............................................................................... 2 
Functional Block Diagram .............................................................. 3 
Specifications..................................................................................... 4 
Timing Characteristics ................................................................ 6 
Absolute Maximum Ratings.......................................................... 11 
Thermal Resistance .................................................................... 11 
ESD Caution................................................................................ 11 
Pin Configuration and Function Descriptions........................... 12 
Typical Performance Characteristics ........................................... 16 
Theory of Operation ...................................................................... 18 
Analog Front End (AFE) ........................................................... 18 
MAC Interface ............................................................................ 19 
Autonegotiation .......................................................................... 20 
Autonegotiation Disabled.......................................................... 20 
Management Interface ............................................................... 20 
MDI Interface.............................................................................. 22 
Reset Operation .......................................................................... 22 
Power-Down Modes .................................................................. 24 
Status LED ................................................................................... 25 
PHY Output Clocks ................................................................... 26 
Power Supply Domains.............................................................. 26 
Hardware Configuration Pins....................................................... 27 
Hardware Configuration Pin Functions.................................. 27 
On-Chip Diagnostics ..................................................................... 31 
Loopback Modes ........................................................................ 31 
REVISION HISTORY
11/2019—Revision 0: Initial Version
Data Sheet
Frame Generator and Checker ................................................. 32 
Cable Diagnostics....................................................................... 33 
Enhanced Link Detection ......................................................... 33 
Start of Packet Indication .......................................................... 33 
Applications Information .............................................................. 35 
System Overview ........................................................................ 35 
REM Switch, fido5200 ............................................................... 35 
Detailed Overview of fido5200 and ADIN1200 .................... 36 
Power Supply............................................................................... 36 
Component Recommendations ............................................... 38 
Power Requirements .................................................................. 39 
Supply Decoupling ..................................................................... 39 
Register Summary .......................................................................... 41 
PHY Core Register Summary................................................... 41 
PHY Core Register Details........................................................ 43 
Subsystem Register Summary .................................................. 71 
Subsystem Register Details ....................................................... 72 
PCB Layout Recommendations.................................................... 77 
PHY Package Layout.................................................................. 77 
Component Placement .............................................................. 77 
MDI, Differential Pair Routing ................................................ 77 
MAC Interface Pins.................................................................... 77 
Power and Ground Planes......................................................... 77 
Layout Guidelines for LFCSP Package .................................... 78 
Outline Dimensions ....................................................................... 79 
Ordering Guide .......................................................................... 79 
Rev. 0 | Page 2 of 79


Features Data Sheet Robust, Industrial, Low Powe r, 10 Mbps and 100 Mbps Ethernet PHY AD IN1200 FEATURES 10BASE-Te/100BASE-TX I EEE® 802.3TM compliant MII, RMII and R GMII MAC interfaces 100BASE-TX RGMII la tency transmit: <124 ns, receive <250 n s 100BASE-TX MII latency transmit: <52 ns, receive <248 ns EMC test standards IEC 61000-4-5 surge (±4 kV) IEC 61000- 4-4 electrical fast transient (EFT) (± 4 kV) IEC 61000-4-6 conducted immunity (10 V) EN55032 radiated emissions (Clas s A) EN55032 conducted emissions (Class A) Unmanaged configuration using multi level pin strapping EEE in accordance w ith IEEE 802.3az Start of packet detect ion for IEEE 1588 time stamp support En hanced link detection Configurable LED Crystal oscillator/clock input: 25 MHz 25 MHz/125 MHz synchronous clock output Small package and wide temperature ran ge 32-lead, 5 mm × 5 mm LFCSP Specifie d for −40°C to +105°C and −40°C to +85°C ambient operation Low power c onsumption 139 mW for 100BASE-TX 3.3 V/2.5 V/1.8 V MAC interface VDDIO supp.
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