SN74LVC1G86 Gate Datasheet

SN74LVC1G86 Datasheet, PDF, Equivalent


Part Number

SN74LVC1G86

Description

Single 2-Input Exclusive-OR Gate

Manufacture

etcTI

Total Page 28 Pages
Datasheet
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SN74LVC1G86
SCES222Q – APRIL 1999 – REVISED JUNE 2017
SN74LVC1G86 Single 2-Input Exclusive-OR Gate
1 Features
1 ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
• Qualified from –40°C to +125°C
• Supports 5-V VCC Operation
• Inputs Are Over Voltage Tolerant up to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4 ns at 3.3 V and 15-pF load
• Low Power Consumption, 10-µA Maximum ICC At
85°C
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode, and Back-
Drive Protection
• Available in the Texas Instruments
NanoFree™ Package
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
2 Applications
• Wireless Headsets
• Motor Drives and Controls
• TVs
• Set-Top Boxes
• Audio
3 Description
The SN74LVC1G86 device performs the Boolean
function Y = AB + AB in positive logic. This single 2-
input exclusive-OR gate is designed for 1.65-V to 5.5-
V VCC operation.
If the input is low, the other input is reproduced in
true form at the output. If the input is high, the signal
on the other input is reproduced inverted at the
output. This device has low power consumption with
maximum tpd of 4 ns at 3.3 V and 15-pF capacitive
load. The maximum output drive is ±32-mA at 4.5 V
and ±24-mA at 3.3 V.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current back flow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G86DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74LVC1G86DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74LVC1G86DRL
SOT (5)
1.60 mm × 1.20 mm
SN74LVC1G86YZP
DSBGA (5)
1.44 mm × 0.94 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
EXCLUSIVE OR
=1
Copyright © 2017, Texas Instruments Incorporated
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.
These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be
shown at any two ports.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC1G86
SN74LVC1G86
SCES222Q – APRIL 1999 – REVISED JUNE 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics, CL = 15 pF ...................... 6
6.7 Switching Characteristics, CL = 30 pF or 50 pF........ 6
6.8 Operating Characteristics.......................................... 6
6.9 Typical Characteristics .............................................. 6
7 Parameter Measurement Information .................. 7
8 Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Function Table .......................................................... 9
9 Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1 Receiving Notification of Documentation Updates 13
12.2 Community Resources.......................................... 13
12.3 Trademarks ........................................................... 13
12.4 Electrostatic Discharge Caution ............................ 13
12.5 Glossary ................................................................ 13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (September 2015) to Revision Q
Page
• Changed YZP (DSBGA) package pinout diagram and added DSBGA column ..................................................................... 3
• Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down
(Ioff), and Over-voltage Tolerant Inputs sections..................................................................................................................... 8
Changes from Revision O (December 2013) to Revision P
Page
• Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision N (January 2007) to Revision O
Page
• Updated document to new TI data sheet format. ................................................................................................................... 1
• Removed Ordering Information table. .................................................................................................................................... 1
• Updated Ioff in Features. ......................................................................................................................................................... 1
• Updated operating temperature range. .................................................................................................................................. 4
2 Submit Documentation Feedback
Copyright © 1999–2017, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G86


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity SN74LVC1G86 SCES222Q – APRIL 1999 – REVISED JUNE 2017 SN74LVC1G86 Single 2-Input Exclusive-OR Gate 1 Fea tures •1 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) • Qualified from –40°C to +125°C • Supports 5-V VCC Operation • Inp uts Are Over Voltage Tolerant up to 5.5 V • Supports Down Translation to VCC • Maximum tpd of 4 ns at 3.3 V and 1 5-pF load • Low Power Consumption, 10 -µA Maximum ICC At 85°C • ±24-mA O utput Drive at 3.3 V • Ioff Supports Partial-Power-Down Mode, and Back- Driv e Protection • Available in the Texas Instruments NanoFree™ Package • La tch-Up Performance Exceeds 100 mA Per J ESD 78, Class II 2 Applications • Wir eless Headsets • Motor Drives and Con trols • TVs • Set-Top Boxes • Aud io 3 Description The SN74LVC1G86 devic e performs the Boolean function Y = AB + AB in positive logic. This single 2input exclusive-OR gate is designed .
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