SN74LVC1G86

Product Folder Order Now Technical Documents Tools & Software Support & Community SN74LVC1G86 SCES222Q – APRIL 1999 – REVISED JUNE 2017 SN74LVC1G86 Single 2-Input Exclusive-OR Gate 1 Features 1 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) Qualified from –40°C to +125°C Supports 5-V VCC Operation Inputs Are Over Voltage Tolerant up to 5.5 V Supports Down Translation to VCC Maximum tpd of 4 ns at 3.3 V and 15-pF load Low Power Consumption, 10-µA Maximum ICC At 85°C ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode, and Back- Drive Protection Available in the Texas Instruments NanoFree™ Package Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II 2 Applications Wireless Headsets Motor Drives and Controls TVs Set-Top Boxes Audio 3 Description The SN74LVC1G86 device performs the Boolean function Y = AB + AB in positive logic. This single 2input exclusive-OR gate is designed for 1.65-V to 5.5V VCC operation. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum tpd of 4 ns at 3.3 V and 15-pF capacitive load. The maximum output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing da...