SN74LVC1G80 Flip-Flop Datasheet

SN74LVC1G80 Datasheet, PDF, Equivalent


Part Number

SN74LVC1G80

Description

Single Positive-Edge-Triggered D-Type Flip-Flop

Manufacture

etcTI

Total Page 28 Pages
Datasheet
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SN74LVC1G80
SCES221S – APRIL 1999 – REVISED NOVEMBER 2016
SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop
1 Features
1 Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Supports Down Translation to VCC
• Maximum tpd of 4.2 ns at 3.3 V
• Low Power Consumption, 10-µA Maximum ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
• Test and Measurement
• Enterprise Switching
• Telecom Infrastructure
• Motor Drives
3 Description
This single positive-edge-triggered D-type flip-flop is
designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output
on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the level at the output.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G80DBV SOT-23 (5)
2.90 mm × 1.60 mm
SN74LVC1G80DCK SC70 (5)
2.00 mm × 1.25 mm
SN74LVC1G80YZP DSBGA (5)
1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
CLK 2
CC
C
TG
4Q
C
D 1 TG
C
TG
C
C
TG
C
(1) TG - Transmission Gate
C
C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC1G80
SN74LVC1G80
SCES221S – APRIL 1999 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements: TA = –40°C to +85°C ............ 6
6.7 Timing Requirements: TA = –40°C to +125°C .......... 6
6.8 Switching Characteristics: TA = –40°C to +85°C, CL =
15 pF .......................................................................... 7
6.9 Switching Characteristics: TA = –40°C to +85°C, CL =
30 pF or 50 pF ........................................................... 7
6.10 Switching Characteristics: TA = –40°C to +125°C,
CL = 30 pF or 50 pF ................................................... 7
6.11 Operating Characteristics........................................ 7
6.12 Typical Characteristics ............................................ 8
7 Parameter Measurement Information .................. 9
8 Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1 Documentation Support ........................................ 15
12.2 Receiving Notification of Documentation Updates 15
12.3 Community Resources.......................................... 15
12.4 Trademarks ........................................................... 15
12.5 Electrostatic Discharge Caution ............................ 15
12.6 Glossary ................................................................ 15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision R (December 2013) to Revision S
Page
• Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Added max junction temperature to the Recommended Operating Conditions table ........................................................... 5
• Added operating free-air temperature for YZP package to the Recommended Operating Conditions table ........................ 5
• Changed RθJA value for DBV package from: 206°C/W to: 243.4°C/W ................................................................................... 5
• Changed RθJA value for DCK package from: 252°C/W to: 278.9°C/W ................................................................................... 5
• Changed RθJA value for YZP package from: 132°C/W to: 136.9°C/W.................................................................................... 5
Changes from Revision Q (January 2007) to Revision R
Page
• Updated document to new TI data sheet format. ................................................................................................................... 1
• Removed Ordering Information table. .................................................................................................................................... 1
• Updated Ioff in Features. ......................................................................................................................................................... 1
• Updated operating temperature range. .................................................................................................................................. 4
• Added ESD warning ............................................................................................................................................................ 15
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Features Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LVC1G80 SCES221S – APR IL 1999 – REVISED NOVEMBER 2016 SN74L VC1G80 Single Positive-Edge-Triggered D -Type Flip-Flop 1 Features •1 Availa ble in the Texas Instruments NanoFree Package • Supports 5-V VCC Operatio n • Inputs Accept Voltages to 5.5 V Supports Down Translation to VCC • Maximum tpd of 4.2 ns at 3.3 V • Low Power Consumption, 10-µA Maximum ICC • ±24-mA Output Drive at 3.3 V • I off Supports Live Insertion, Partial-Po wer-Down Mode, and Back-Drive Protectio n • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protec tion Exceeds JESD 22 – 2000-V Human-B ody Model (A114-A) – 200-V Machine Mo del (A115-A) – 1000-V Charged-Device Model (C101) 2 Applications • Test an d Measurement • Enterprise Switching • Telecom Infrastructure • Motor Dr ives 3 Description This single positiv e-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. When data at the data (D.
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