UT61256 SRAM Datasheet

UT61256 Datasheet, PDF, Equivalent


Part Number

UT61256

Description

32K x 8 BIT HIGH SPEED CMOS SRAM

Manufacture

UTRON

Total Page 12 Pages
Datasheet
Download UT61256 Datasheet


UT61256
Rev. 1.1
UTRON
UT61256
32K X 8 BIT HIGH SPEED CMOS SRAM
FEATURES
Fast access time : 8/10/12/15ns (max.)
Low operating power consumption:
80 mA (typical.)
Single5V power supply
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Package : 28-pin 300 mil skinny PDIP
28-pin 300 mil SOJ
28-pin 330 mil SOP
28-pin 8mm×13.4 mm STSOP
FUNCTIONAL BLOCK DIAGRAM
A4
A3
A14
A13
.
.A12 ROW
DECODER
A7
A6 .
A5
A8
I/O1
...
... I/O
CONTROL
I/O8
...
MEMORYARRAY
512 ROWS × 512 COLUMNS
. ..
COLUMNI/O
COLUMNDECODER
CE LOGIC
WE CONTROL
OE
A11 A9 A10 A2 A1 A0
VCC
VSS
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
VCC
VSS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
GENERAL DESCRIPTION
The UT61256 is a 262,144-bit high speed CMOS
static random access memory organized as
32,768 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT61256 is designed for high-speed system
application. It is particularly suited for use in high
speed and high density system applications.
The UT61256 operates from a signal 5V power
supply and all inputs and outputs are fully TTL
compatible
PIN CONFIGURATION
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
28 Vcc
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
PDIP/SOP/SOJ
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
UT61256
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
P80020

UT61256
Rev. 1.1
UTRON
UT61256
32K X 8 BIT HIGH SPEED CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to VSS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
VTERM
TA
TSTG
PD
IOUT
Tsolder
RATING
-0.5 to +7.0
0 to +70
-65 to +150
1
50
260
UNIT
V
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
TRUTH TABLE
MODE
CE
Standby
H
Output Disable
L
Read
L
Write
L
Note: H = VIH, L=VIL, X = Don't care.
OE WE
XX
HH
LH
XL
I/O OPERATION
High - Z
High - Z
DOUT
DIN
SUPPLY CURRENT
ISB, ISB1
ICC
ICC
ICC
DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = 0to 70)
PARAMETER
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
Operating Power
Supply Current
Standby Power
Supply Current
SYMBOL TEST CONDITION
VIH
VIL
ILI VSS VIN VCC
ILO VSS VI/O VCC
CE =VIH or OE =VIH or WE = VIL
VOH IOH= - 4mA
VOL IOL= 8mA
ICC CE = VIL ,
II/O = 0mA ,Cycle=Min.
-8
- 10
- 12
- 15
ISB CE =VIH
ISB1 CE VCC-0.2V
MIN.
2.2
-0.5
-1
-1
MAX.
VCC+0.5
0.8
1
1
UNIT
V
V
µA
µA
2.4 - V
- 0.4 V
- 190 mA
- 180 mA
- 160 mA
- 140 mA
- 30 mA
- 5 mA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
P80020


Features  Rev. 1.1 UTRON UT61256 32K X 8 BIT HIGH SPEED CMOS SRAM FEATURES Fast ac cess time : 8/10/12/15ns (max.) Low ope rating power consumption: 80 mA (typica l.) Single5V power supply All inputs an d outputs are TTL compatible Fully stat ic operation Three state outputs Packag e : 28-pin 300 mil skinny PDIP 28-pin 3 00 mil SOJ 28-pin 330 mil SOP 28-pin 8m m×13.4 mm STSOP FUNCTIONAL BLOCK DIAG RAM A4 A3 A14 A13 . .A12 ROW DECOD ER A7 A6 . A5 A8 I/O1 ... ... I/O CONTROL I/O8 ... MEMORYARRAY 512 RO WS × 512 COLUMNS . .. COLUMNI/O COLUMN DECODER CE LOGIC WE CONTROL OE A11 A9 A10 A2 A1 A0 VCC VSS PIN DESCRIPTION SYMBOL A0 - A14 I/O1 - I/O8 CE WE OE VCC VSS DESCRIPTION Address Inputs Dat a Inputs/Outputs Chip Enable Input Writ e Enable Input Output Enable Input Powe r Supply Ground GENERAL DESCRIPTION Th e UT61256 is a 262,144-bit high speed C MOS static random access memory organiz ed as 32,768 words by 8 bits. It is fab ricated using high performance, high reliability CMOS technology. T.
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