Document
Data sheet acquired from Harris Semiconductor SCHS167E
November 1997 - Revised October 2004
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241,
CD54/74HC244, CD54/74HCT244
High-Speed CMOS Logic
Octal Buffer/Line Drivers, Three-State
[ /Title (CD74 HC240 , CD74 HCT24 0, CD74 HC241 , CD74 HCT24 1, CD74 HC244 , CD74
Features
Ordering Information
• HC/HCT240 Inverting
• HC/HCT241 Non-Inverting
• HC/HCT244 Non-Inverting
•
Typical Propagation Delay = 8ns CL = 15pF, TA = 25oC for HC240
at
VCC
=
5V,
• Three-State Outputs
• Buffered Inputs
• High-Current Bus Driver Outputs
• Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
PART NUMBER CD54HC240F3A CD54HC244F3A CD54HCT240F3A CD54HCT241F3A CD54HCT244F3A CD74HC240E CD74HC240M CD74HC240M96 CD74HC241E CD74HC241M CD74HC241M96 CD74HC244E CD74HC244M CD74HC244M96 CD74HCT240E CD74HCT240M CD74HCT240M96
TEMP. RANGE (oC)
PACKAGE
-55 to 125
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
-55 to 125
20 Ld PDIP
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld PDIP
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld PDIP
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld PDIP
-55 to 125
20 Ld SOIC
-55 to 125
20 Ld SOIC
Description
The ’HC240 and ’HCT240 are inverting three-state buffers having two active-low output enables. The CD74HC241, ’HCT241, ’HC244 and ’HCT244 are non-inverting threestate buffers that differ only in that the 241 has one activehigh and one active-low output enable, and the 244 has two active-low output enables. All three types have identical pinouts.
CD74HCT240PW CD74HCT240PWR CD74HCT240PWT CD74HCT241E CD74HCT241M CD74HCT241M96
-55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125
20 Ld TSSOP 20 Ld TSSOP 20 Ld TSSOP 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC
CD74HCT244E
-55 to 125
20 Ld PDIP
CD74HCT244M
-55 to 125
20 Ld SOIC
CD74HCT244M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
Pinout
CD54HC240, CD54HCT240, CD54HCT241, CD54HC244, CD54HCT244 (CERDIP)
CD74HC240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244 (PDIP, SOIC) CD74HCT240, (PDIP, SOIC, TSSOP)
TOP VIEW
241 240 244
241 244 240
1OE 1A0 2Y3 1A1 2Y2 1A2 2Y1 1A3 2Y0 GND
1OE 1 1A0 2 2Y3 3 1A1 4 2Y2 5 1A2 6 2Y1 7 1A3 8 2Y0 9 GND 10
20 VCC VCC 19 2OE (241) 2OE (240, 244) 18 1Y0 1Y0 17 2A3 2A3 16 1Y1 1Y1 15 2A2 2A2 14 1Y2 1Y2 13 2A1 2A1 12 1Y3 1Y3 11 2A0 2A0
Functional Diagram
2 1A0
4 1A1
6 1A2
8 1A3
11 2A0
13 2A1
15 2A2 240 17 AND 2A3 244 241
1OE 1OE 2OE 2OE
1 19
241 AND 244 240
18 1Y0 1Y0
16 1Y1 1Y1
14 1Y2 1Y2
12 1Y3 1Y3
9 2Y0 2Y0
7 2Y1 2Y1
5 2Y2 2Y2
3 2Y3 2Y3
VCC = 20 GND = 10
2
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 69oC/W
M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . 58oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . 83oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . ..