PEEL22LV10AZ Logic Datasheet

PEEL22LV10AZ Datasheet, PDF, Equivalent


Part Number

PEEL22LV10AZ

Description

CMOS Programmable Electrically Erasable Logic

Manufacture

ICT

Total Page 10 Pages
Datasheet
Download PEEL22LV10AZ Datasheet


PEEL22LV10AZ
Commercial/Industrial
PEEL™ 22LV10AZ-25 / I-35
CMOS Programmable Electrically Erasable Logic Device
Features
Low Voltage, Ultra Low Power Operation
- Vcc = 2.7 to 3.6 V
- Icc = 5 µA (typical) at standby
- Icc = 1.5 mA (typical) at 1 MHz
- Meets JEDEC LV Interface Spec (JESD8-B)
- 5 Volt tolerant inputs and I/O’s
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super set of standard PLDs
- Pin and JEDEC compatible with 22V10
- Ideal for battery powered systems
- Replaces expensive oscillators
General Description
The PEEL22LV10AZ is a Programmable Electrically
Erasable Logic (PEEL) SPLD (Simple Programmable
Logic Device) that operates over the supply voltage
range of 2.7V-3.6V and features ultra-low, automatic
"zero" power-down operation. The PEEL22LV10AZ is
logically and functionally similar to ICT's 5V
PEEL22CV10A and PEEL22CV10AZ. The "zero power"
(25 μA max. ICC) power-down mode makes the
PEEL22LV10AZ ideal for a broad range of battery-
powered portable equipment applications, from hand-
held meters to PCMCIA modems. EE-
reprogrammability provides both the convenience of
product fast reprogramming for product development
and quick personalization in manufacturing, including
Engineering Change Orders.
Architectural Flexibility
- Enhanced architecture fits in more logic
- 133 product terms x 44 input AND array
- 12 inputs and 10 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear, synchronous preset
- Independent output enables
- Programmable clock; pin 1 or p-term
- Programmable clock polarity
- 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC
- Schmitt triggers on clock and data inputs
Schmitt Trigger Inputs
- Eliminates external Schmitt trigger devices
- Ideal for encoder designs
The differences between the PEEL22LV10AZ and
PEEL22CV10A include the addition of programmable
clock polarity, p-term clock, and Schmitt trigger input
buffers on all inputs, including the clock. Schmitt trigger
inputs allow direct input of slow signals such as
biomedical and sine waves or clocks. Like the
PEEL22CV10A, the PEEL22LV10AZ is a pin and
JEDEC compatible, logical superset of the industry
standard PAL22V10 SPLD Figure 1. The
PEEL22LV10AZ provides additional architectural
features that allow more logic to be incorporated into
the design. The PEEL22LV10AZ architecture allows it
to replace over twenty standard 24-pin DIP, SOIC,
TSSOP and PLCC packages.
Figure 1 - Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
DIP
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I
TSSOP
I
4 3 2 1 28 27 26
5 25
I/O
I6
24 I/O
I7
23 I/O
NC 8
22 NC
I9
21 I/O
I 10
20 I/O
I 11
19 I/O
12 1314 15 1617 18
PLCC
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I
SOIC
Figure 2 - Block Diagram
CLK MUX (Optional)
I/CLK
I
I
I
I
I
I
I
I
I
I
I
PEEL TM
"AND"
ARRAY
133 Terms
X
44 Inputs
SP
AC
OE
MACRO
CELL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SP = SYNCHRONOUS PRESET
AC = ASYNCHRONOUS CLEAR
OE = OUTPUT ENABLE
1 04-02-037D

PEEL22LV10AZ
132
0
2
I/CLK*
(2)
9
10
I*
(3)
20
21
I*
(4)
33
34
I*
(5)
48
49
I*
(6)
65
66
I*
(7)
82
83
I*
(9)
97
98
I*
(10)
110
111
I*
(11)
121
124
I*
(12)
130
131
I*
(13)
PEELTM 22LV10AZ
(N
ASYNCHRONOUS CLEAR
(TOA LLMA CROCE LLS)
MACRO
CELL
I/O*
(27)
MACRO
CELL
I/O*
(26)
MACRO
CELL
I/O*
(25)
MACRO
CELL
I/O*
(24)
MACRO
CELL
I/O*
(23)
MACRO
CELL
I/O*
(21)
MACRO
CELL
I/O*
(20)
MACRO
CELL
I/O*
(19)
MACRO
CELL
I/O*
(18)
MACRO
CELL
I/O*
(17)
SYNCHRONOUS PRESET
(TOA LLMA CROCE LLS)
* Schmitt Trigger Inputs
I*
(16)
Figure 3 - PEEL22LV10AZ Logic Array Diagram
2 04-02-037D


Features Commercial/Industrial PEEL™ 22LV10AZ- 25 / I-35 CMOS Programmable Electricall y Erasable Logic Device Features • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 µA (typ ical) at standby - Icc = 1.5 mA (typica l) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-B) - 5 Volt tolerant inputs and I/O’s • CMOS Electrically Eras able Technology - Superior factory test ing - Reprogrammable in plastic package - Reduces retrofit and development cos ts • Application Versatility - Replac es random logic - Super set of standard PLDs - Pin and JEDEC compatible with 2 2V10 - Ideal for battery powered system s - Replaces expensive oscillators Gene ral Description The PEEL22LV10AZ is a P rogrammable Electrically Erasable Logic (PEEL) SPLD (Simple Programmable Logic Device) that operates over the supply voltage range of 2.7V-3.6V and features ultra-low, automatic "zero" power-down operation. The PEEL22LV10AZ is logical ly and functionally similar to ICT's 5V PEEL22CV10A and PEEL22CV10AZ. The .
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