CDCDB2000 Buffer Datasheet

CDCDB2000 Datasheet, PDF, Equivalent


Part Number

CDCDB2000

Description

20-Output Clock Buffer

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download CDCDB2000 Datasheet


CDCDB2000
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CDCDB2000
SNAS787 – NOVEMBER 2019
CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
1 Features
1 20 LP-HCSL outputs with integrated 85-output
terminations
• 8 hardware output enable (OE#) controls
• Additive phase jitter after DB2000QL filter:
< 0.08ps rms
• Supports PCIe Gen 4 and Gen 5 Common Clock
(CC) and Individual Reference (IR) architectures
– Spread spectrum-compatible
• Cycle-to-cycle jitter: < 50 ps
• Output-to-output skew: < 50 ps
• Input-to-output delay: < 3 ns
• 3.3-V core and IO supply voltages
• Hardware-controlled low power mode (PD#)
• Side-Band Interface (SBI) for output control in
PD# mode
• 9 selectable SMBus addresses
• Power consumption: < 600 mW
• 6-mm × 6-mm, 80-pin TLGA/GQFN package
2 Applications
Microserver & tower server
Storage area network & host bus adapter card
Network attached storage
Hardware accelerator
3 Description
The CDCDB2000 is a 20-output LP-HCSL,
DB2000QL compliant, clock buffer capable of
distributing the reference clock for PCIe Gen 1-5,
QuickPath Interconnect (QPI), UPI, SAS, and SATA
interfaces. The SMBus, SBI, and 8 output enable pins
allow the configuration and control of all 20 outputs
individually. The CDCDB2000 is a DB2000QL
derivative buffer and meets or exceeds the system
parameters in the DB2000QL specification. The
CDCDB2000 is packaged in a 6-mm × 6-mm
TLGA/GQFN package with 80 leads.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDCDB2000
TLGA (80)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
CDCDB2000 System Diagram
PCIe Gen 4-5 LP-HCSL
Clock
Generator
CDCDB2000
20x LP-HSCL Output Buffer
20
LP-HCSL
PPCPCIPeCIePCIPePCPPIHeCPICHeYPIHIYeePHYPHDYHYeYvice
SMBus
Control
Side-Band
Interface
OE#
Control
Control Interface
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

CDCDB2000
CDCDB2000
SNAS787 – NOVEMBER 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information .................................................. 7
6.5 Electrical Characteristics........................................... 7
6.6 Timing Requirements ................................................ 9
6.7 Typical Characteristics ............................................ 12
7 Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
7.5 Programming .......................................................... 15
7.6 Register Maps ........................................................ 18
8 Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application ................................................. 24
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Examples................................................... 27
11 Device and Documentation Support ................. 30
11.1 Device Support .................................................... 30
11.2 Receiving Notification of Documentation Updates 30
11.3 Support Resources ............................................... 30
11.4 Trademarks ........................................................... 30
11.5 Electrostatic Discharge Caution ............................ 30
11.6 Glossary ................................................................ 30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
November 2019
REVISION
*
NOTES
Initial release.
2 Submit Documentation Feedback
Product Folder Links: CDCDB2000
Copyright © 2019, Texas Instruments Incorporated


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity CDCDB2000 SNAS787 – NOVEMBER 2019 CDCDB2000 DB2000QL-Compliant 20-Ou tput Clock Buffer for PCIe Gen 1 to Gen 5 1 Features •1 20 LP-HCSL outputs with integrated 85-Ω output terminati ons • 8 hardware output enable (OE#) controls • Additive phase jitter afte r DB2000QL filter: < 0.08ps rms • Sup ports PCIe Gen 4 and Gen 5 Common Clock (CC) and Individual Reference (IR) arc hitectures – Spread spectrum-compatib le • Cycle-to-cycle jitter: < 50 ps Output-to-output skew: < 50 ps • I nput-to-output delay: < 3 ns • 3.3-V core and IO supply voltages • Hardwar e-controlled low power mode (PD#) • S ide-Band Interface (SBI) for output con trol in PD# mode • 9 selectable SMBus addresses • Power consumption: < 600 mW • 6-mm × 6-mm, 80-pin TLGA/GQFN package 2 Applications • Microserver & tower server • Storage area networ k & host bus adapter card • Network attached storage • Hardware accelerator 3 Description The CDCDB.
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